Processor Design Actuals (Pre-Midterm)

Question 1

DEFINE: The von Neumann Model.

Answer 1

The model of a computer as the interactive components of main memory, processing and storage.

Question 2

What functions can a Turing machine compute, of all the functions in existence?

Answer 2

Any that can be computed mechanically.

Question 3

What stages does the classic RISC pipeline have?

Answer 3

1) Fetch.
2) Decode.
3) Execute.
4) Memory.
5) Writeback.

Question 4

What two major constraints does pipeline staging in processor design have to contend with?

Answer 4

1) Circuit timing, i.e. how to minimize delays, speed up the clock, keep processing order intact.
2) Memory Access Latency, i.e. the delay of querying main memory, outer caches.

Question 5

Why aren’t there only three stages of processors, Fetch, Execute, and Memory?

Answer 5

The Execute step takes much too long, so it must be split up to speed up the clock.

In other words, the pipeline is unbalanced.

Question 6

What is the goal of pipelining stages in the processor?

Answer 6

To parallelize the functions it performs, maximizing throughput.