Superscalar and Out-of-Order Processors Flashcards

1
Q

In a processor without superscalar, what is the optimal effective CPI?

A

1.

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2
Q

When we measure for AMAT in processors, what metric are we generally using as a unit?

A

CPI or IPC.

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3
Q

DEFINE: An n-way Superscalar Processor.

A

A processor that can run multiple pipelines to parallelize processing, so as to increase throughput.

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4
Q

What prevents us from achieving theoretically optimal CPI in a superscalar system?

A

The natural portion of code that is inherently unparallelizable. I.E. Amdahl’s Law.

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5
Q

In an n-way superscalar processor, what is the theoretically optimal CPI?

A

1/n CPI.

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6
Q

TRUE/FALSE: Superscalar processing systems are an example of manycores in action.

A

FALSE. Superscalar works within a single core.

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7
Q

What are the two major concerns with in-order superscalar processors?

A

1) We can only stall for many data hazards, as forwarding would break the dependency.
2) We need increased complexity and chip resource allocation to handle it.

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8
Q

DEFINE: VLIW.

A

Very Long Instruction Word. An ISA that utilizes long instruction space to process multiple instructions at once.

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9
Q

What’s historically been the problems with VLIW?

A

It makes the compiler’s job very hard due to required parallelization logic, isn’t backwards compatible, and has very complex hazard management. Also, Amdahl’s Law.

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10
Q

I write the following code:

int foo = 0;
for {int i = 0; i < 256; ++i) {
foo = 2 * foo + 1;
}

return foo;

I have a 256-way superscalar out-of-order processor, and I have a magical branch predictor that always guesses correctly. I optimize my code, allowing for loop unrolling, but it still doesn’t run well. Why is this?

A

Data hazards still exist within each iteration, so the parallelization creates a ton of stalling.

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11
Q

DEFINE: Out-of-order processor.

A

A processor that utilizes scheduling to process instructions out-of-order, while monitoring and minimizing hazards.

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12
Q

Why do superscalar processors tie-in well with out-of-order processors?

A

Superscalars are looking for groups of n instructions each to run simultaneously; Out-of-order processors allow them to look for upcoming instructions to maximize throughput in this regard.

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13
Q

Which pipeline stage is the Scheduler added to in out-of-order processors?

A

The Decode stage.

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14
Q

What kind of data structure represents dependencies in a set of instructions?

A

The Instruction Dependence Graph.

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15
Q

Why is out-of-order processing more appealing than VLIW in the software space?

A

It’s transparent in its parallelization. The compiler for VLIW has to manage dependencies, the microarchitecture for OoO manages them instead.

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16
Q

What’s the most common type of hazard for out-of-order processors to manage?

A

Read-after-write hazards.

17
Q

What techniques do we have to deal with read-after-write dependencies when operating with an out-of-order processor?

A

After utilizing the scheduler optimally, we can only stall.

18
Q

TRUE/FALSE: We can do arithmetic and logical operations parallel in Out-of-order frameworks, but we have to commit those operations In-Order to preserve data coherency.

19
Q

TRUE/FALSE: Unfortunately, using a Scheduler for out-of-order processing adds a ton of overhead due to its O(n log n) schema (as a result of the heaps it uses).

A

FALSE. Thanks to Tomasulo’s algorithm, we can get a constant rate of regulation.

20
Q

DEFINE: Write-after-read hazards.

A

In out-of-order processing, when an earlier instruction reads a value that was overwritten after a later instruction writes it.

21
Q

DEFINE: Write-after-write hazards.

A

In out-of-order processors, when a later write instruction is then overwritten by an earlier write instruction.

22
Q

DEFINE: Read-after-read hazards.

A

Not a thing. In out-of-order, so long as no write comes in between, reading after a later read isn’t a problem.

23
Q

How can we resolve write-after-write and write-after-read hazards without stalling in out-of-order processors?

A

Using Register Renaming, a.k.a. Shadow Registers.

24
Q

If the named registers are defined by the ISA, which registers are used by register renaming?

A

Physical Registers. As opposed to the named registers (architectural registers), these are not specified by the ISA.

25
Q

DEFINE: SIMD.

A

Single Instruction, Multiple Data. A processor technique that uses a single ISA instruction on many pieces of data. An example is multiplying every value in an array by 2.

26
Q

Of VLIW and SIMD, which makes a greater impact in today’s processors?

A

SIMD. It is used in laptops and smartphones to this day. That said, most of the time it must be called explicitly.

27
Q

What modern capability is SIMD especially good for?

A

Machine learning, because of the prevalence of matrix operations.