Memory

Question 1

What is a logic level?

Answer 1

In analogue, 1s and 0s are divided by a threshold voltage. SO whilst 0 and 1 are convenient abstractions they do not reflect reality.

Question 2

What are the main criteria for designing a memory system?

Answer 2

Rapid data access and it should take as little space as possible.

Question 3

What assumptions must be made to model digital discrete circuits as networks?

Answer 3

The nodes are unidirectional, instantaneous, isopotential nets interconnecting devices.

Question 4

How are digital ‘networks’ analysed?

Answer 4

Events (logic transitioned) are generated on the outputs at some future date in response to events asserted on the inputs.

As such analysis is centred on an event queue; a list of events ordered by time.

Question 5

How is the system state of a discrete system represented?

Answer 5

The state can be summarised as the logic values in the nets and the event queue, i.e. events that will happen.

Question 6

What happens when you assert an input?

Answer 6

Logic values don’t propagate instantaneously, although there will be an output change, for a brief time, the event is hidden from the device, but it is still part of the stae.

Question 7

How are logic drivers modelled?

Answer 7

Logic drivers can be modelled as a voltage source with an ‘internal’ impedance.

Question 8

What effect does modelling the driven gate as a resistor have?

Answer 8

Since the driven gate is a resistor, it means that the voltage value on the interconnect is loaded. This means that if multiple gates read from the same interconnect, they may pull down the voltage value, leading to a misrepresentation of the intended logic value.

Question 9

What does fanout measure?

Answer 9

Fanout is a measure of the max number of gates an output can drive before the voltage value is pulled down to the point where the voltage may be incorrectly read.

Question 10

What happens when interconnects are driven at high speeds?

Answer 10

The interconnect begins to behave more like a transmission line, The signal can be sent, reach the destination and reflect. The reflected signal returns after bouncing off the origin leading to a second logic event.

Question 11

What is the forbidden zone in circuits?

Answer 11

The forbidden zone refers to either

(0threshold < V < 1threshold)

Or,

out of range (< 0V or > Vcc)

Question 12

How does CMOS deal with voltages in the forbidden zone?

Answer 12

CMOS devices appear to behave as simple threshold devices so it can be assumed that voltages less than 0 are treated as logic ‘0’ whilst voltages greater than 1_{<strong>threshold</strong>} are treated as logic ‘1’. For voltages in between manufacturers make no promises.

Question 13

How does TTL deal with the forbidden zone?

Answer 13

Holding the voltage at 1V will lead to a 1MHZ oscillation on the output, the exact value depends on the system

Thus max transit time, may be specified, as a measure of how fast you are expected to transit through the zone.

Question 14

Describe the logic states high and low

Answer 14

These are ‘disconnected but still have a value’.
They are capable of being read, like a 0 or 1, but will not fight if connected to a forcing
value. 0, 1, and X are the low impedance equivalents of L, H and Z.

Question 15

Describe how the effective output impedance relates to logic values?

Answer 15

The effective output impedance of the driving gates: for ‘0’, ‘1’ and ‘X’, R_force is as low as can be made practical; the corresponding fanout is high because the low value of R_force allows V_high (or V_low) to be asserted easily on the driven gates. For ‘H’, ‘L’ and ‘Z’, the output impedance (R_weak) is quite high so that if any other gate asserts a ‘0’ ‘1’ or ‘X’, it easily overcomes the high impedance

version.

Question 16

How are events generated?

Answer 16

Outputs are generated in response to changes on inputs

Question 17

How do you determine the difference between 1 and high?

Answer 17

To detect the difference between ‘1’ and ‘H’, . You have to have some means of loading the signal and measuring
d(signal)/d(load).

As measuring the voltage is insufficient to tell the difference.

Question 18

Describe high impedance Z in computing

Answer 18

The voltage value is usually stored on some parasitic capacitance and will decay with time. This might sound a
bit tenuous, but it is the fundamental underlying physical principle of DRAM.

A ‘control’ or bus-driver gate have (conventional) data inputs, plus a ‘control’ input, which may be used to put the output into a high impedance state.

Question 19

Describe the conflict logic state

Answer 19

This is an abstract logic state that unambiguously indicates a problem. It may be derived, for example, if two non-high impedance gates are connected together.

If they both assert the same value, there
is no problem: the drive capability is increased, If the two gates attempt to assert different low-impedance states (‘0’ and ‘1’, for example), then the resultant logic value will depend on the relative values of the two output impedances, but more importantly the current flowing through the two output circuits can
be arbitrarily high - the physical behaviour goes way outside the modelling intent, and in
some logic families device destruction will result. Even if a device can withstand such an insult transiently, the lifetime will be considerably compromised. Ideally, a simulation would tell you this.

Question 20

Describe X (Don’t Know) State

Answer 20

This is a low-impedance signal (forcing) but we don’t know what the value is. Again, it cannot occur in reality - a ‘0’ is a ‘0’, a ‘1’ is a ‘1’, but a ‘X’ will be either a ‘0’ or a ‘1’.

Its existence may or may not indicate a problem; if it propagates through a system it is indicative of subtle (i.e. bad) design.

Like the conflict, you cannot measure it directly, but
also like the conflict, you want to know if you have one.

Question 21

Describe U, uninitialised

Answer 21

This is again something you cannot measure in reality, it is a way for a
simulation to say “nothing that has ever happened has caused me to compute a value for
this signal”. Which begs the question “why is it here?”

Question 22

Should you have more logic states?

Answer 22

Yes, VHDL has eleven distinct logic states, for example - but the more states, the more information you can extract about your design, for only a modest increase in compute.

Question 23

What is the source of the Z persistence?

Answer 23

Most of the ‘unseen’ components that make up a system - nets, pins and so on -have a
parasitic capacitance associated with them. This capacitance stores charge which is the source.

Question 24

Effect of capacitance on alogic driver

Answer 24

To assert a logic value usually means the driver has to
inject or remove that charge. This takes time and requires energy. It is easier, from a practical perspective, to produce a driver that is good at either injection or removal, as opposed to both.

Question 25

What are the goals for memory design

Answer 25

* To make the user believe processes are executing simultaneously * To make each process appear infinite memory is available and can be accessed infinitely quickly.

Question 26

Describe the memory hierarchy

Answer 26

The memory hierarchy refers to the order of primacy for memory, i.e. which memory is used first.. Disk→Memory→Cache→Register

Question 27

What is swapping in Memory?

Answer 27

• The OS stores a queue of processes waiting to execute. • As space becomes available, processes are loaded. When a process finishes, it is removed. • A process may be swapped out if stalled (e.g. waiting for I/O).

Question 28

Describe the idea of optimum swapping

Answer 28

Optimum swapping refers to maintaining a balance between too little and too much swapping. Too much and the processor is spending too much time with memory transfers. Too little, stalled processes aren't removed at the correct time.

Question 29

What is partitioning?

Answer 29

Partitioning is simply a method of splitting memory into pieces. There are two types, fixed size and variable size.

Question 30

Describe Fixed Size Partitioning

Answer 30

Fixed-size memory partitions: Easy to administer (logarithmic distribution is usually best)

Question 31

Describe Variable Size Partitions

Answer 31

Variable-size memory partitions: Memory allocated as required. Fragmentation makes it harder to load incoming processes This leads to memory wastage..

Question 32

Define Process Topology

Answer 32

Refers to what processes are running at what time.

Question 33

Describe Physical Address

Answer 33

Physical addresses refer to absolute locations in memory.

Question 34

Describe Logical Addresses

Answer 34

Logical addresses are relative to the address of the beginning of the program.

Question 35

What is paging?

Answer 35

Paging is the process of dividing the memory of a process into fixed-size pages. Whilst physical memory is in turn divided into frames.

Question 36

How are pages mapped onto frames

Answer 36

Pages can be mapped non-contiguously to frames, and so does not result in memory gaps, unlike with partitioning. Noncontiguous meaning, not placed in a consecutive manner.

Question 37

Pages and Logical Addressing

Answer 37

Logical Addressing is more complicated, as • For a process, a single offset is not enough anymore. • Each process has a page table. • Logical addresses now refer to a page, and the page table translates the base address (logical page) to the physical address (frame)

Question 38

Why are page tables useful?

Answer 38

They are vital for logical addressing. As processes are divided into multiple pages. Pages that require a corresponding logical address for safe storage.

Question 39

How is swapping used with pages?

Answer 39

Pages, not processes, are swapped in and out. Thus, we've created the illusion of "infinite" memory, from the perspective of the process. However, a paging supervisor is required for controlling swap rate.

Question 40

Describe Mapping Logical to physical addressing

Answer 40

Logical addresses, which are used by software to reference sections of memory used by a process, function. differently in a paging system. Logical addresses refer to a page number, which is used as a key in the page table. The page table identifies the frame, from which a base address can be derived. The base address is combined with the offset to obtain the full physical address.

Question 41

What is Page Thrashing? Why is this bad?

Answer 41

Page thrashing is when page faults happen too often. This refers to when a process wants a page that has been swapped out. The OS needs to go fetch it. This is a problem as the processor spends a lot of time re/mapping pages to frames, as opposed to computing.

Question 42

Page Table is Swapped Out

Answer 42

One method is, each logical memory access can require two physical accesses: 1st search through memory if page table is swapped out Then, look up data using page table, however, this method is slow so, Translation Lookaside Buffer(TLB) is used. The TLB is a cache that stores page table entries.

Question 43

What is the Translation Lookaside Buffer?

Answer 43

Cache which stores recent page table entries used as pages can be swapped out.

Question 44

Purpose of virtual memory

Answer 44

To pre-emptively get the required data into the most accessible place, without the user having to care.

Question 45

Where can a page table be?

Answer 45

* The TLB * Main memory * Disk

Question 46

Where can the data be stored in?

Answer 46

* Memory cache * Main memory * Disk

Question 47

Describe Segmentation

Answer 47

Segmentation is another memory management mechanism The application splits memory into segments of variable size at compile time (unlike paging, where the user only sees one contiguous block). • The compiler produces addresses of the form {segment,oset} • The linker reconciles this with the memory subsystem. • Each segment has different access writes and privileges: - Processes can be run in isolation, safely. (Segmentation Fault) - Self-modification can be prevented (Harvard). - Data/cache can be shared between processes.

Question 48

How common is segmentation

Answer 48

Most x86 machines use segmentation with paging.

Question 49

How is segmentation implemented with paging?

Answer 49

Segmentation can be combined with paging. The compiler divides the program into segments at compile time, and the paging supervisor divides each segment into pages at run time. A page table exists for each segment, and entries are stored in the translation lookaside buer as before

Question 50

Aims of Cache Systems

Answer 50

• Provide access speed close to that of the fastest memory. • Provide capacity close to that of the most capacious memory. • The cache contains a local copy of parts of the main memory. • If the CPU wants some memory in the cache, it is returned quickly. • If the CPU wants some memory, not in the cache, the cache fetches it.

Question 51

What do caches store?

Answer 51

The cache contains a local copy of parts of the main memory.

Question 52

Are there levels to cache?

Answer 52

Yes, the levels of caches depend on access speed and memory size.

Question 53

Structure of Memory Vs Cache

Answer 53

Memory is divided into blocks Caches are divided into lines Blocks and lines both store words. We assume lines and blocks are the same sizes. Each line has a tag corresponding to a block. Memory has more blocks than the caches have lines

Question 54

Can caches be filled and fetched from at the same time?

Answer 54

Yes, caches can be filled and fetched form in parallel as they typically involve different processes.

Question 55

Are cache misses errors?

Answer 55

No, at times they must happen such as the first time a program or process is run. As if not run before then the process will not be stored in the cache.

Question 56

Are caches always shared?

Answer 56

No, caches are often split into levels based on the speed of access and size of memory. In addition, these levels may be divided into instruction caches and data caches.

Question 57

Define Block in memory

Answer 57

Block: A set of words in main memory.

Question 58

Define Line in Memory

Answer 58

Line: A tagged entry in the cache, which holds a set of words.

Question 59

Define tag in memory

Answer 59

Tag: An ld associated with the cache line and its contents.

Question 60

Define cache hit

Answer 60

**Cache hit**: Process wants to read from memory, and the cache has it, resulting in a faster lookup compared to a cache miss.

Question 61

Define Cache Miss

Answer 61

**Cache miss**: Process wants to read from memory, but the cache does not have it, so the cache has to fetch it, resulting in a slower lookup than a cache hit.

Question 62

Why are caches separated?

Answer 62

In part because different processes require different access patterns. As such more efficient for different caches to correspond to different access patterns. Caches can be designed based on the type of instruction used for the cache.

Question 63

What are tradeoffs to consider for caches

Answer 63

Should the cache behave more like a register or memory, i.e. access speed vs storage size

Question 64

What are mapping functions?

Answer 64

Caches are smaller than memory, so blocks need to be mapped onto caches. A mapping function tells the cache line to which memory block is related. There are three types: - Direct - Associative - Set Associative

Question 65

What is direct mapping?

Answer 65

• Each block of main memory maps onto only one line. A set of blocks are designated to the same line.

Question 66

Benefits and flaws of direct mapping

Answer 66

• Quick to calculate which line a given block should be placed in Cache line ID = Block number (in main memory) % Number of lines in the cache • Cache Thrashing: High cache miss rate - different blocks are addressed by the process, which are alternately mapped and evicted. With direct mapping this can easily happen

Question 67

How to break direct mapping?

Answer 67

To cause thrashing can make alternate references to blocks in the same set. As the blocks are never stored in the cache at the same time since each line can only hold one memory block.

Question 68

What is associative mapping?

Answer 68

• Any block can go into any cache line. • The tag is the address of the block that's currently loaded. • To check if the cache holds a block, the cache needs to (simultaneously) compare all cache tags with the desired block address. • Expensive lookup, but flexible for a greater variety of access patterns.

Question 69

How to break associative mapping?

Answer 69

Break by a loop. The number of blocks in the loop should be greater than the number of lines in the cache.

Question 70

What is set-associative mapping?

Answer 70

* Compromise between direct and associative. * The cache is divided into a set of subcaches. * Each memory block can go into only one subcache (ala direct), but it can into any line of that subcache (ala associative). * As subcache size → cache size (i.e. only one subcache), the cache becomes **fully associative.** * As subcache size → 1 (i.e. each subcache holds only one line), the cache becomes **fully direct.**

Question 71

What are replacement algorithms?

Answer 71

Replacement Functions are used to determine which line is overwritten when a new block is loaded. Algorithms include: - Least recently used - First-in, first-out - Least frequently used - Random

Question 72

What is cache coherence?

Answer 72

The problem of keeping main memory and the cache synchronised.

Question 73

What is cache coherence?

Answer 73

The problem of keeping main memory and the cache synchronised.

Question 74

What problems are associated with cache coherence?

Answer 74

**Read access:** No problem with a single access pathway, but DMA exists. **Write access:** If a cache line has been written to (dirty), it must be pushed to the main memory before it's replaced.

Question 75

What are the solutions to cache coherence?

Answer 75

**Write Through**: Update main memory whenever a cache line is written. **Write Back**: Update main memory whenever a cache line is evicted.

Question 76

What is write through?

Answer 76

* All write operations are performed in parallel. * All modules with cache access must monitor all reads to maintain coherency. This leads to substantial memory traffic!

Question 77

What is Write Back?

Answer 77

* When a line is modified, a "dirty" bit is set, and the main memory is only updated when a "dirty" line is replaced. * All access through one cache.

Question 78

What are the solutions to cache coherency for multiprocessor machines?

Answer 78

Bus watching, Hardware transparency: and Non-cacheable segments:

Question 79

Describe Bus watching

Answer 79

A solution to cache coherency in multiprocessors In a write-through system, any write to the main memory causes the immediate removal of cache lines containing the clobbered data.

Question 80

Describe Hardware transparency

Answer 80

A solution to cache coherency in multiprocessors Used for write-through systems, each write to main memory causes an immediate update of all cache lines. Doesn't delete and re-load entire cache.

Question 81

What are non-cacheable segments

Answer 81

A solution to cache coherency in multiprocessors Prevent caching of certain regions of (shared) memory.

Question 82

Large Vs Small Line Sizes

Answer 82

Smaller blocks/lines better exploit locality, result in more fetch/replace operations, and have less data transfer for those operations. Larger Lines mean less fetch operations are required however, means less lines can be used in a cache. In general line size is between 8-32 bytes.

Question 83

What is cache granularity?

Answer 83

How to and if to use cache levels, i.e. how to stagger cache levels.

Question 84

Why use multilevel caches?

Answer 84

Different Caches are suitable for different processes.

Question 85

Why use a unified/Split Cache? Split meaning between instruction and data not in storage size

Answer 85

* Unified cache has a better overall hit rate because the code/data imbalances even out. * For fast (pipeline) architectures, a Harvard cache eliminates data/code bus contention (in a pipeline, data and code can be requested out of order).

Question 86

How do caches and virtual memory interact?

Answer 86

• Cache systems and virtual memory systems operate largely orthogonally to each other - the virtual memory system exists \after" the caching system. Addresses may be taken from the Virtual memory, however, caches are not aware of pages, they simply see memory blocks.

Question 87

How do caches relate to Translation Lookaside Buffer(TLB)?

Answer 87

• The interactions between cache systems and the translation lookaside buer (TLB) are more complicated; either the tags in the cache hold - physical addresses (in which case they need to be translated by the TLB prior to lookup), or - logical addresses (in which case cache tags need to be kept in coherence with the state of the TLB)

Question 88

How do disks relate to memory analysis?

Answer 88

* They typically have their own processor and memory. * They also have a layered cache system - certain "bits of magnetic space" are easier to get at than others. * Spatial locality really matters. * They typically have their own RAM caches.

Question 89

How is the response generated?

Answer 89

The response is generated as a sequence of events appearing on the output of each gate

Question 90

How has the performance of modern systems affected the analysis of systems

Answer 90

Can't as easily assume voltage signals reach gates at the same time. A difference in path length causes a significant time difference.

Question 91

The voltage at receiver equation

Answer 91

V_r =( V_wR_r)/(R_w +R_r)

Question 92

What happens if R_r → infinity

Answer 92

V_r = V_w R_r \>\> R_w

Question 93

What happens if R_r → 0?

Answer 93

V_r →0, with R_w \>\> R_r

Question 94

How can the voltage/logic level be corrupted?

Answer 94

VOltage van be pulled down to 0 if R_r→0.

Question 95

What is TTL?

Answer 95

Transistor–transistor logic (TTL) is a logic family built from bipolar junction transistors. Its name signifies that transistors perform both the logic function (the first "transistor") and the amplifying function (the second "transistor"), as opposed to resistor–transistor logic (RTL) or diode–transistor logic (DTL).

Question 96

Can boolean algebra always apply to a bus?

Answer 96

No, when the nodes are driven in different directions, simple ones and zeros don't describe the outputs of the bus. SO we also observe the impedances.

Question 97

What should you do if multiple sources are driving a bus?

Answer 97

For multiple sources sat all other drives to weak values states i.e. R_weak is high impedance, so source with low forcing impedance dominates for the bus.

Question 98

What is a passive pull-up/pull-down device?

Answer 98

Basically, a resistor is a device that without extra Work, will pull up or pull down the voltage of the net. Designed to have said voltage easily overwritten by active inputs to the net.

Question 99

What are the benefits of passive pullup/pulldown devices?

Answer 99

Boost efficiency of up-down behaviour. Allows the driver to be smaller, and more efficient as only either removes charge or only adds charge.

Question 100

How are pull up/ pull down incorporated into a device?

Answer 100

The effect is created simply by connecting a resistor between the net and either ground (for passive pull-down) or the supply rail (for passive pull up). Often rather than a resistor a MOS transistor with the gate and source shorted, which requires no extra processing steps which makes better use of the space..

Question 101

How is the virtual driver designed?

Answer 101

1: Two inputs the same, output:=input 2: Forcing 0 and forcing 1 is a conflict 3: Forcing 0 and X might be a conflict 4: Conflicts propagate: anything and a conflict is a conflict 5: Z is always overridden ?: 1 for pull up, 0 for pull-down

Question 102

What are the logic families? Features

Answer 102

* RTL - resistor transistor logic (now obsolete) * DTL - diode transistor logic (now obsolete) * TTL - transistor transistor logic (extremely common, becoming less so) * ECL - emitter coupled logic (fast, heavy on power) * MOS - metal oxide semiconductor (low power) * CMOS - complementary metal oxide semiconductor (even less power) * BiCMOS - Bipolar CMOS (fast, low power, good driving capability) * GaAs - Gallium Arsenide (very fast) * SiGe - Silicon Germanium heterojunction (currently fastest)

Question 103

What is the fastest current logic family?

Answer 103

* Fastest logic made to date: * SiGe bipolar heterojunction stacked current logic * Clocks at 80GHz * fT 450GHz * Gate delay 6 ps

Question 104

Flaws of SiGe bipolar heterojunction stacked current logic

Answer 104

•The logic thresholds are different for each input to each gate

Question 105

Describe Static RAM Cell

Answer 105

● Large (poor packing density) ● Fast ● Power hungry ● Persistent (the data is stable as long as the power is maintained) Bistable memory.

Question 106

Describe Dynamic RAM Cell

Answer 106

Holds Bit Value for roughly 1 millisecond ## Footnote * Highest packing density of all memory topologies * Three components form the cell * Two are parasitic

Question 107

Describe Response of non-inverting amplifier

Answer 107

Ideal, linear increase, however, Output saturates after a certain value as output voltage reaches supply voltage..

Question 108

Describe the response of inverting analogue amplifier.

Answer 108

Negative Linear. Saturates at high voltage, near supply, and low voltage when close to 0.

Question 109

The equation for output of inverting analogue amplifier

Answer 109

Question 110

What happens when we combine two amplifiers back to back

Answer 110

connect them back-to-back so that the input of each is driven by the output of the other, we can superpose the transfer characteristics, and if the stage gains are high enough, we get the situation shown in the figure.

Question 111

What happens if the stage gain when combining the two amplifiers is not high enough?

Answer 111

If the gains are insufficient for the transfer characteristics to intersect like this, we get a situation where there exists just one stable equilibrium point, at the single crossing point. (The transition between these two states occurs when the slope of the linear region = 1, i.e. Rb = βRc)

Question 112

Define Paging

Answer 112

Paging is a mechanism to separate data and can be used to implement a virtual memory system. It is **architecture-sympathetic** ie. architecture side memory management.

Question 113

Define Segmentation

Answer 113

Segmentation is a memory management mechanism by which data/instructions can be split into segments to divide programs in a user-sympathetic manner.

Question 114

How are multiple pages implemented?

Answer 114

Page directory is implemented, stores page tables and is never swapped out. It is stored in the OS block.