Intro to pipeline

Question 1

Formule

Answer 1

1.CPU time = IC x Clock cycle x CPI

2.Execution time (pipe) =
k x tc x 1 +(n-1) x tc

3.Execution time (unpipe) = k x tc x n

4.Speedup =
Ex time(unpipe)/Ex time(pipe)

5.Speedup (with stalls) =
pipeline depth / 1+ pipeline stall cycles per instr

6.Speedup(with stalls)=
    CPI X K /(CPI + stalls per cycle)

Question 2

Design issues

Answer 2

1. Clock cycle of all stages cannot be same
   Solution: Make Length of each stage equal to Length of Longest stage or slowest Stage

2.Pipeline Register Overhead
* pipeline registers that are set between two stages with the names of the stages.
* They serve the purpose of transferring outputs produced in a phase to the subsequent phase in the multi-cycle implementation.
*must be large enough to contain all data moving from one phase to
the following one
* combination of pipeline register delay and the clock skew
* Pipeline registers delay: Setup time that triggers a write or when data input
changes and propagation delay to the clock.
* Clock skew: Maximum delay between when the clock arrives at any two
registers.

Question 3

Explain ARM 5 stage
Fetch - [IF]

Answer 3

• Fetch - [IF]
  1. fetched from memory and placed in the instruction pipeline.
  2. Update the PC to the next sequential PC by adding 4 to PC

Question 4

Explain ARM 5 stage
Decode – [ID]

Answer 4

• Decode – [ID]
  1. instruction is decoded and register operands read from the register files.
  2. Do the equality test on the registers as they are read, for a possible branch.
  3. Sign extend the offset field of the instruction in case it is needed.
  4. Compute the possible branch target address by adding the sign-extended offset to the incremented PC.
  5. the branch can be completed by the
  end this stage by storing the branch target address into the PC if condition yielded true.

Question 5

Explain ARM 5 stage
Execute - [EX]

Answer 5

• Execute – [EX]
  1. ̥The ALU operates on the operands prepared in the previous cycle, performing of the three functions
  depending on the instruction type.
  –Memory Reference:
  –Register – Register ALU instruction:
  –Register – Immediate ALU instruction:

Question 6

Explain ARM 5 stage
Memory Access - [MEM]

Answer 6

Memory Access-[MEM]
1. ̥Data memory is accessed if required.Otherwise the ALU result is simply buffered for one cycle.
2. LOAD, the memory does a read using effective address computed in the previous cycle.
3. STORE, then the memory writes the data from the second register read using the effective address.

Question 7

Explain ARM 5 stage
Write Back - [WB]

Answer 7

• Write back – [WB]
  1. ̥The result generated by the instruction is written back to the register file.
  2. data may come either from memory system [for
  LOAD], or from the ALU [ for an ALU instruction].