ARM architecture Flashcards

1
Q

RISC features incorporated by ARM

A
  1. A load-store architecture.
  2. Fixed-length 32-bit instructions.
  3. 3-address instruction formats.
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2
Q

Explain the organization of ARM

(7)

A
  1. 3 stage pipline - fectch,decode, execute
  2. The register bank, which stores the processor state.
    * Two read ports and One write port - to access any register
    * Plus an additional read port and an additional write port that give special access to r1
  3. The barrel shifter, which can shift or rotate one operand by any number of bits.
  4. The ALU, which performs the arithmetic and logic functions required by the instruction set.
  5. The address register and incrementer, which select and hold all memory addresses and generate sequential addresses when required.
  6. The data registers, which hold data passing to and from memory.
  7. The instruction decoder and associated control logic.
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3
Q

What are the modes ?

A
  1. User
  2. FIQ
  3. IRQ
  4. Supervisor
  5. Abort
  6. Undefined
  7. System
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4
Q

Describe the Status register

A

divided into four fields
* flags(f) - 4bits + 4bits
1. N-negative: set to 1 - prev result neg
2. Z-zero:set to 1 - prev result zero
3. C-carry:set to 1 - produce carryout
4. V-overflow:set to 1 - prev overflow to sign bit
* Status(s) - 8 bits
* extension(x) - 8 bits
* control(c) - 8 bits
1. ̥I / F - disable bits - I=1 disable IRQ/F =1 disable FIQ
2. T bit - thumb mode only -> T=1 in thumb state

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5
Q

Short note on thumb instruction

A

Thumb is a 16-bit instruction set

  • Optimized for code density from C code (~65% of ARM code size)
  • Improved performance from memory with a narrow data bus
  • Subset of the functionality of the ARM instruction set
  • Only Low Registers R0-R7 are used
  • Constants are of limited size.
  • Inline barrel shifter not used.
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6
Q

Explain the two kinds of status registers

A

Current Program Status Register: CPSR
1. monitor & control internal operations.
2. The current status of the program under execution, such as, result of current execution instruction is zero/ -ve are captured here.

Saved Program Status Register: SPSR
1. Processor, While Shifting one mode to another mode, CPSR will be copied to SPSR.
2. SPSR will be copied back to CPSR when it return back to previous mode.

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7
Q

Explain the features of ARM ISA

(6)

A
  • All ARM instructions are 32 bits wide.
  • The load-store architecture.
  • 3-Address data processing instructions (that is, the two source operand registers and the result register are all independently specified).
  • Conditional execution of every instruction.
  • Inclusion of very powerful load and store multiple register instructions.
  • Ability to perform a general shift operation and a general ALU operation
    in a single instruction that executes in a single clock cycle.
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8
Q

RISC features rejected by ARM

A

Register windows
1. RISC processors incorporated a large number of registers.
2. Procedure entry and exit instructions moved the visible ‘window’ to give each procedure access to new registers.
3. reducing the data traffic between the processor and memory resulting from register saving and restoring.
4. priciple prob- large chip area occupied by the large number of registers.
5.rejected on cost grounds.

Delayed branches
1. ̥Branches cause pipelines problems since they interrupt the smooth flow of
instructions.
2.using delayed branches where the
branch takes effect after the following instruction has executed.
3.Work well on single issue pipelined processors
4.But, do not scale well to super-scalar implementations & can interact badly with branch prediction mechanisms.

Single-cycle execution of all instructions
1. ̥ARM executes most data processing instructions in a single clock cycle,
2. simple load or store instruction requires at least two memory accesses.
3. only possible with separate data
and instruction memories.

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