Hazards

Question 1

Types of hazards

Answer 1

• Structural
  1. ̥Due to structture of pipeline
  2. h/w can’t support combo of instr in pipeline needing same resources
• Data
  1. ̥due to data dependencies b/w instr
  2. instr depends on the result of prior instr still in pipeline
• Control
  1. ̥due to control instr
  2. pipelining of brances & other instr taht change the PC

Question 2

What are stalls ?

Answer 2

• inserting one or more “bubbles” in the pipeline until the hazard is resolved
• To do this, hardware or software must detect that a hazard has occurred
• Disadv
  1. ̥is a waste cycle
  2. adds to pipeline delay and increases CPI
  3. affetcs performance of pipeline architecture

Question 3

what is structural hazard ?

Answer 3

1. resource conflict arises due to a hardware resource being required by more than one instruction in a single cycle̥
2. when a pipelined machine has a shared single-memory for data and instructions.(IF = MEM)
3. when a machine has only one register file write port(Skip MEM stage for add/sub..)
4. when a machine has overlapping of read and write(Overlap ID & WB)

Question 4

IF = MEM = Unified Mem operation

Answer 4

sol 1 : stall
Sol 2 :Replication of resources
–Split Memory (Instruction Memory & Data Memory)
–Harvard Memory Architecture

Question 5

WB Vs WB:
AND instr has no mem
so WB -WB conflict

Answer 5

Sol 1 : stall
Sol 2 : °Let all the instruction follow all stages, AND may take longer than usual

Question 6

ID VS WB

Answer 6

Partitioning/Overlapping
1st half of the cycle Reg Write
2nd half of the same cycle Reg Read

Question 7

What are the types of data dependencies?

Answer 7

1. ̥RAW: Read after Write or Flow dependency (True Dependency)
   ~~~
   add r1,r2,r3
   sub r4,r1,r3
   ~~~
2. WAR: Write after Read or anti-dependency (Anti Dependency)
   ~~~
   sub r4,r1,r3
   add** r1**,r2,r3
   mul r6,r1,r7
   ~~~
   sol : rename register
3. WAW: Write after Write (Output Dependency)
   ~~~
   sub** r1,r4,r3
   add r1**,r2,r3
   mul r6,r1,r7
   ~~~
   sol: rename register
   .

Question 7

How to solve RAW ?

Answer 7

1. ̥S/W - reorder instr
2. s/w- insert independent instr or no-ops
3. h/w- insert bubbles
4. h/w- data forwarding

Question 8

Explain Data forwarding

Answer 8

incomplete

Question 9

Problems with 1-bit predictor

Answer 9

• Aliasing Problem
  branches with same lower order bits will reference the same entry,causing mutual prediction
• Shortcomings with loops
  Always mispredict twice for every loop
  Mispredict upon exiting a loop, since this is a surprise
  If we repeat the loop, we’ll miss again since we’ll predict, branch not taken