intro to cache

Question 1

1.

What is memory latency?

Answer 1

time it takes to transfer a word of data to or from mem

Question 2

what is mem bandwidth?

Answer 2

no of bits or bytes that can be transferred in one sec

Question 3

Explain cache

Answer 3

1. ̥architectural arrangement which makes the main memory appear faster to the processor than it really is.
2. based on the property of computer programs known as “locality of reference”.

Question 4

explain locality of reference

Answer 4

Analysis of programs indicates that many instructions in localized areas of a program are executed repeatedly during some period of time, while the others are accessed relatively less frequently.

Temporal locality (locality in time):
* if an item is referenced, it will tend to be referenced again soon.
* Whenever an instruction or data is needed for the first time, it should be
brought into a cache. It will hopefully be used again repeatedly.

Spatial locality (locality in space):
* if an item is referenced, items whose
addresses are close by will tend to be referenced soon.
* Instead of fetching just one item from the main memory to the cache at a
time, several items that have addresses adjacent to the item being
fetched may be useful.

Question 5

explain load-through or early restart

Answer 5

1. ̥Block of words containing this requested word is transferred from the memory.
   2.After the block is transferred, the desired word is forwarded to the processor
   3.The desired word may also be forwarded to the processor as soon as it is transferred without waiting for the entire block to be transferred.

Question 6

three categories six optimizations can be vlassified

Answer 6

1. ̥Reducing miss rate
   * larger block size
   * larger cache size
   * higher associativity
2. Reducing miss penalty
   * multilevel cache
   * read priority over write
3. reducing time to hit in the cache
   * avoding address translation when indexing the cache

Question 7

Threee categories of misses are:

Answer 7

1. ̥Compulsory
   * very first access to block cannot be in the cache. So, the block must be brought into the cache.
2. Capacity
   * If the cache cannot contain all the blocks needed during execution of a program, capacity misses [ in addition to compulsory misses] will occur because of blocks being discarded and later retrieved.
3. Conflict
   * If the block placement strategy is set associative or direct mapped, conflict misses [in addition to compulsory and capacity misses ] will occur because a block may be discarded and later retrieved if too many blocks map to its set. These misses are also called collision
   misses.

Question 8

What are the six cache optimizations?

Answer 8

First Optimization: Larger Block Size to Reduce Miss Rate.

Second Optimization: Larger Caches to Reduce Miss Rate.

Third Optimization: Higher Associativity to Reduce Miss Rate.

Fourth Optimization : Multilevel Caches to Reduce Miss Penalty.

Fifth Optimization: Giving Priority to Read Misses over Writes to Reduce Miss Penalty.

Sixth Optimization: Avoiding Address Translation during Indexing of the Cache to Reduce Hit Time.

Question 9

give adv and disadv of 1st optimization

Answer 9

Advantage:
1. Satisfy Spatial Locality
2. Reduces Compulsory Misses
Disadvantage:
1. Increase Miss Penalty ( Bus width Issues)̥
2. Increase Conflict Miss, as Number of Cache Blocks reduces due increase in
Block Size.
3.May bring useless data into cache as Spatial Locality cannot be maintained in
entire program consistently.

Question 10

give adv and disadv of 2nd optimization

Answer 10

Advantage:
1. Reduces Capacity Miss̥
2. Can accommodate large memory footprint.̥

Disadvantage
Increases Hit Time
High Cost, Area and Power

Question 11

give adv and disadv of 3rd optimization

Answer 11

Higher Associativity to Reduce Miss Rate
* Fully Associative cache are best, as no replacement is required till cache is full.
* Set Associative cache balances the Search Time and Replacement.

Advantage:
1.Reduce Conflict Miss
2.Reduce Miss Rate and Eviction rate.

Disadvantage:
1.Increases Hit Time (Due to increase in search time by comparing each TAG)
2.Complex design than Direct Map.

Question 12

explain the 4th optimization

Answer 12

First level cache can be small enough to match the clock cycle time of the
processor.

Second level cache be can be large enough to capture many accesses that would go to main memory, thus reducing miss penalty.

Multilevel cache will complicate performance analysis.

Question 13

explain the 6th optimization

Answer 13

Virtually Indexed & Physically Tagged

Do not wait for VA to PA translation.

Extract Index information from Virtual Address

Extract Tag Information from the Physical Address.