i/o and bus architecture Flashcards
explain i/o bus
1.exists special h/w components b/w CPU and peripherals to supervise and synchronize all the input and output transfers
2. consists of data lines,address line and control lined
3. i/o bus from processor is attached to all peripherals interface
4. to communicate with a particular device ,processor places a devie address on adddress lines
explain memory mapped i/o device interface
- Same address decoder selects memory and I/O ports.
- Some memory address space is occupied by the I/O devices.
- All data transfer instructions to / from memory can be used to transfer to/from I/O devices.
- Processor need not have separate instructions for I/O.
explain i/o mapped device interface
- Separate instructions for I/O data transfer [ IN / OUT].
- Processor signal identifies whether a generated address refers to memory or I/O device.
- Separate address decoder for selecting memory and I/O ports.
- Complete memory address space can be utilized.
what are some data transfer techniques?
- ̥Programmed i/o :
* CPU executes a program and that transfers data b/w i/o device and mem
* synchronous : fixed rate of transfer
* asynchronous : handshanking - polling for sending and receiving data
* interrupt driven
2.Direct mem access(DMA) :
* An external controller directly transfers data between I/O device and Memory without CPU intervention.
explain interrupt driven data transfer
- ̥CPU initiates the data transfer and proceeds to perform some other task.
- When I/O module is ready for data transfer, it informs the CPU by activating a signal (Interrupt request).
- The CPU suspends the task it was doing, services the request from the device and return back to the task it was doing.
Advantages
* CPU time is not wasted by polling the device
* CPU time is required only during the data transfer plus some overheads for transferring and returning the control.
What happens when an interrupt request arrives?
* At the end of the execution of the current instruction, PC and the status register contents are saved in the stack automatically.
* Interrupt is acknowledged, interrupt vector is obtained based which the control transfers to the appropriate ISR.
* After handling the interrupt, the ISR executes a special instruction return from interrupt(RTI).
How is interrupt nesting handled?
- A device D0 has interrupted and the CPU is servicing the (executing the ISR) device D0.
- In the meantime, device D1 has interrupted.
- Two possible scenarios are here:
1. ̥D1 will interrupt the ISR for D0, get processed first, and then the ISR for device D0 will be resumed.
2. Disable the interrupt system automatically whenever an interrupt is
acknowledged.
explain polling technique
Each device can have a status bit whether the device has interrupted?
CPU can poll the status bit to check for the device which has interrupted.
– Daisy Chain Technique
In Daisy chain technique, INTR line is common to all the devices.
INTA line is connected in a daisy chain fashion [ as shown].
This allows to propagate serially through the devices.
A device when it receives INTA, passes the signal to the next device only if it has
not interrupted.
Else, it stops the propagation of INTA and puts the identifying code on the data
bus.
Thus the device that is electrically closest to the CPU will have the highest
priority.
Exaplain Direct mem access
an interrupt handler was used and the I/O machine produces all the signals that the CPU produce, then the I/O machine can bypass the information alienates to central processing unit and hence increases the speed.
Cycle Stealing Process: Traditionally it is a method of accessing RAM or bus without
interfering with the CPU.
adv:
can permit the CPU to run at full speed
without any delay if external devices access memory not actively participating in the CPU’s current activity and complete the operations before any possible CPU conflict.
explain what is universal bus architecture
- data interface used with computers enabling the computer to send and receive data as well as providing power to some peripherals
- When a peripheral is attached to the USB network, the host communicates with the device.(enumeration)
To learn its identity
To discover which device driver is required
Explain PCI bus architecture
- local computer bus for attaching hardware devices in a computer.
- Any PCI device may initiate a transaction.
- First, it must request permission from a PCI bus arbiter on the motherboard.
- arbiter grants permission to one of the requesting devices.
- initiator begins the address phase by broadcasting a 32- bit address plus a 4-bit command code, then waits for a target to respond.
- All other devices examine this address and one of them responds a few cycles later.
Explain SCSI Architecture
- Provided as a bridge between hard disk low-level interface and a host computer
- Standard Interface and communication protocol for connecting computer peripherals.
- increase performance and deliver faster
- address upto 8 devices (0 to 7).
- Based on the Client Server Architecture
Clients are Initiators – creates(begins)and sends SCSI commands to the target.
Servers are Targets – Collection of logical units – carries out the requested task.
Explain AMBA
- open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC).
- facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.
- that enables IP reuse if
Flexibility:
Wide Adaption:
Compatibility:
Support:
