digital quiz 1 nmos pmos cmos Flashcards
Fabrication Steps
BBFG
SESEO
SN
SBS
DC
LON
PSP
SS
WCESP
− Start with blank wafer.
− Build inverter from the bottom up.
− First step will be to form the n- well.
− Grow SiO₂ on top of Si wafer.
− Spin on photoresist
− Expose photoresist through n-well mask.
− Strip off exposed photoresist.
− Etch oxide with hydrofluoric acid.
− Only attacks oxide where resist has been exposed
− Strip off remaining photoresist.
− Necessary so resist doesn’t melt in the next step.
− N-well is formed with diffusion or ion implantation.
− Strip off the remaining oxide using HF.
− Back to bare wafer with n-well.
− Subsequent steps involve similar to series of steps.
− Deposit very thin layer of gate oxide.
− Chemical Vapor Deposition (CVD) of silicon layer.
− Use same lithography process to pattern polysilicon.
− Use oxide and masking to expose where n+ dopants should be diffused or implanted.
− N-diffusion forms NMOS source, drain and n-well contact.
− Patterns oxide and forms n+ regions.
− Self-aligned process where gate blocks diffusion.
− Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing.
− Historically dopants were diffused.
− Usually ion implantation today.
− But regions are still called diffusion.
− Strip off oxide to complete patterning step.
− Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact.
− Now we need to wire together the devices.
− Cover chip with thick field oxide.
− Etch oxide where contact cuts are needed.
− Sputter on aluminum over whole wafer
-Pattern to remove excess metal, leaving wires.
design require cycles of top - down design followed by bottom up redesign
DBRLCL
specifcation
behaviour
register transfer
logic
circuit
layout
CMOS IC Design Process
(SHSLSRFT)
− Defining circuit specifications
− Hand calculations and schematics
− Circuit simulations
− Circuit layout
− Simulations including parasitics
− Reevaluation of circuit inputs and outputs
− Fabrication
− Testing
