CPU Structure, Function and Performance Flashcards
what happens in the fetch
data and instructions are fetched from main memory
what is the address bus
this transmits memory addresses specifying where data is to be sent to
what is a data bus
used or transporting data and instructions between components
what happens in the decode stage
this is where the the fetched instruction is decoded
execute phase
this is where the decoded instruction is executed
control units
controls the activities of the CPU and the flow of data
what does the clock speed mean
time taken for one clock cycle to complete
what does CPU cores allow u to do
allows multiple instructions to be processed at the same time
what is pipelining
where the output of one stage is the input for another
what is the Harvard architecture
where the programs instructions are stored separately in memory
what are the disadvantages of the Harvard architecture
memory is not dynamic as one half is used for data and the other for instruction
what are the advantages of the Harvard architecture
quicker execution as data and instructions can be fetched in parallel
what is CISC
complex instruction set computers, can execute many instructions in only one line of code
what is RISC
reduced instruction set computers, can only execute one line of code at a time
what is an example of a parallel system
a GPU it has lots of different processors which work in parallel to complete repetitive tasks
Current instruction Register
holds the current instruction being executed by the CPU
what does the MAR do
holds the address of the location that is to be fetched from memory
what does the MDR do
holds the data that has been read or data that has to be written
what does the PC do
holds the address of the next instruction to be executed
what does the PC do
holds the address of the next instruction to be executed
what are buses
parallel wires which connect components inside the CPU
what happens in the fetch relating to registers
address from the PC is copied to the MAR
what happens in the decode relating to registers
the contents in the CIR are split into operand and opcode
what is the difference between level 1 cache and level 3
level1 cache is faster than level 3
what are the advantages of von neumann architecture
it is cheaper to develop as control unit is easier to design
programs can be optimised in size
what are the advantages of the Harvard architecture
quicker execution as data and instruction can be fetched in parallel
memories can be different sizes which can make more efficient use of space
what does the GPU do with respect to its processors
graphics processing unit which contains lots of different processors working in parallel making it very efficient to complete various REPETITITVE TASKS (image processing)
why is pipelining possible on the RISC processor
it is possible since each instruction takes one clock cycle and it is simpler to execute therefore they can processed in parallel
what is the difference between parallel systems and multicore systems
multicore systems use multiple cores to process instruction in parallel
parallel systems ONLY USE 1 core to process tasks simultaneously
what is the purpose of the CU
synchronizes data transfer between registers
