CPU Structure, Function and Performance Flashcards

1
Q

what happens in the fetch

A

data and instructions are fetched from main memory

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2
Q

what is the address bus

A

this transmits memory addresses specifying where data is to be sent to

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3
Q

what is a data bus

A

used or transporting data and instructions between components

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4
Q

what happens in the decode stage

A

this is where the the fetched instruction is decoded

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5
Q

execute phase

A

this is where the decoded instruction is executed

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6
Q

control units

A

controls the activities of the CPU and the flow of data

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7
Q

what does the clock speed mean

A

time taken for one clock cycle to complete

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8
Q

what does CPU cores allow u to do

A

allows multiple instructions to be processed at the same time

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9
Q

what is pipelining

A

where the output of one stage is the input for another

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10
Q

what is the Harvard architecture

A

where the programs instructions are stored separately in memory

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11
Q

what are the disadvantages of the Harvard architecture

A

memory is not dynamic as one half is used for data and the other for instruction

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12
Q

what are the advantages of the Harvard architecture

A

quicker execution as data and instructions can be fetched in parallel

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13
Q

what is CISC

A

complex instruction set computers, can execute many instructions in only one line of code

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14
Q

what is RISC

A

reduced instruction set computers, can only execute one line of code at a time

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15
Q

what is an example of a parallel system

A

a GPU it has lots of different processors which work in parallel to complete repetitive tasks

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16
Q

Current instruction Register

A

holds the current instruction being executed by the CPU

17
Q

what does the MAR do

A

holds the address of the location that is to be fetched from memory

18
Q

what does the MDR do

A

holds the data that has been read or data that has to be written

19
Q

what does the PC do

A

holds the address of the next instruction to be executed

20
Q

what does the PC do

A

holds the address of the next instruction to be executed

21
Q

what are buses

A

parallel wires which connect components inside the CPU

22
Q

what happens in the fetch relating to registers

A

address from the PC is copied to the MAR

23
Q

what happens in the decode relating to registers

A

the contents in the CIR are split into operand and opcode

24
Q

what is the difference between level 1 cache and level 3

A

level1 cache is faster than level 3

25
Q

what are the advantages of von neumann architecture

A

it is cheaper to develop as control unit is easier to design
programs can be optimised in size

26
Q

what are the advantages of the Harvard architecture

A

quicker execution as data and instruction can be fetched in parallel
memories can be different sizes which can make more efficient use of space

27
Q

what does the GPU do with respect to its processors

A

graphics processing unit which contains lots of different processors working in parallel making it very efficient to complete various REPETITITVE TASKS (image processing)

28
Q

why is pipelining possible on the RISC processor

A

it is possible since each instruction takes one clock cycle and it is simpler to execute therefore they can processed in parallel

29
Q

what is the difference between parallel systems and multicore systems

A

multicore systems use multiple cores to process instruction in parallel
parallel systems ONLY USE 1 core to process tasks simultaneously

30
Q

what is the purpose of the CU

A

synchronizes data transfer between registers