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Microprocessors > Chapter 9 - JEP > Flashcards

Chapter 9 - JEP Flashcards

1
Q

__-pin dual in-line packages

A

40

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2
Q
  • DIPs
A

o Dual in-line packages

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3
Q
  • Which microprocessor uses M/IO
A

8086

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4
Q
  • Which microprocessor uses IO/M
A

8088

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5
Q

Power Supply Requirements in Voltage and Tolerance

A

5V +-10% tolerance

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6
Q

o 8086 Max current supply

A

360 mA

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7
Q

o 8088 Max current supply

A

340 mA

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8
Q

Temperature of operation

A
  • Between 32 and 180 F
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9
Q

Logic 0 V max (input char.)

A

 0.8 V max

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10
Q

Logic 1 V max (input char.)

A

 2.0 V max

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11
Q

Max current (input char.)

A

+- 10uA

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12
Q

Logic 0 V max (output char.)

A

 0.45 V max

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13
Q

Logic 0 I max (output char.)

A

 2.0 mA max

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14
Q

Logic 1 V max (output char.)

A

 2.4 V max

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15
Q

Logic 1 I max (output char.)

A

 -400 uA max

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16
Q

Pin Connection (8086 & 8088)
o Address/data bus lines are multiplexed address data bus of 8088

A
  • AD7 – AD0
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17
Q

Pin Connection (8086 & 8088)
o Address Latch Enable

A
  • ALE
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18
Q

Pin Connection (8086 & 8088)
o Address bus provides the upper-half memory address bits that are present throughout bus cycle

A
  • A15-8
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19
Q

Pin Connection (8086 & 8088)
o Address/data bus lines compose the upper multiplexed address/data bus on the 8086
o A15-A8 when ALE is Logic 1

A
  • AD15-AD8
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20
Q

Pin Connection (8086 & 8088)
o Address/status bus bits are multiplexed to provide address signals A19-A16, S6-S3

A
  • A19/S6 – A16/S3
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21
Q

RD

A

Read

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22
Q

Pin Connection (8086 & 8088)
o When read signal is L0, data bus is receptive to data from the memory or I/O devices connected

A
  • RD
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23
Q

Pin Connection (8086 & 8088)
o Insert wait states into the timing of the microprocessor

A
  • READY
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24
Q

o Request a hardware interrupt

A
  • INTR
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25
Q
  • INTR
A

o Interrupt request

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26
Q

o Input that is tested by the WAIT instruction

A
  • TEST
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27
Q
  • NMI
A

o Non-maskable interrupt

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28
Q

o Similar to INTR except it does not check to see whether the IF flag is L1

A
  • NMI
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29
Q

o Causes the microprocessor to reset itself if this pun is held high for 4 clocking periods

A
  • RESET
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30
Q
  • CLK
A

o Clock

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31
Q

o Provides the basic timing signal

A
  • CLK
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32
Q

o Power supply input provides a 5V, +- 10% signal

A
  • VCC
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33
Q

o Return for the power supply

A
  • GND
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34
Q
  • MN/MX
A

o Minimum/maximum

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35
Q

o Selects either min mode or max mod operation for the microprocessor

A
  • MN/MX
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36
Q
  • BHE S7
A

o Bus high enable

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37
Q

o Enable the most significant data bus bits during a read or write operation

A
  • BHE S7
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38
Q

o Selects memory or I/O

A
  • IO/M (8088) or M/IO (8086)
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39
Q

o Indicates that the microprocessor address bus contains either a memory address or an I/O port address

A
  • IO/M (8088) or M/IO (8086)
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40
Q
  • WR
A

o Write line

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41
Q

o Strobe that indicates that the 8086/8088 is outputting a data to a memory or I/O device

A
  • WR
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42
Q
  • INTA
A

o Interrupt acknowledge

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43
Q

o Response to the INTR input pin

A
  • INTA
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44
Q
  • ALE
A

o Address latch enable

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45
Q

o Shows that address/data bus contains address information

A
  • ALE
46
Q
  • DT/R
A

o Data transmit/receive

47
Q

o Shows that the microp data bus is transmitting (DT/R = 1) or receiving (DT/R = 0) data

A
  • DT/R
48
Q
  • DEN
A

o Data enable

49
Q

o Activates external data bus buffers

A
  • DEN
50
Q

o Hold input
o Requests a direct memory access

A
  • HOLD
51
Q
  • DMA
A

o Direct memory access

52
Q
  • HLDA
A

o Hold acknowledge

53
Q

o Indicates that the 8086/8088 has entered the hold state

A
  • HLDA
54
Q

o Equivalent to the So pin in max mode operation of the microp

A
  • SS0
55
Q

o Status bits indicate the function of the current bus cycle

A
  • S2, S1, and S0
56
Q
  • RQ/ GT1 and RQ/GT0
A

o Request/grant pins

57
Q

o Request direct memory access during max mode operation

A
  • RQ/ GT1 and RQ/GT0
58
Q

o Used to lock peripherals off the system

A
  • LOCK
59
Q
  • QS1 and QS0
A

o Queue status

60
Q

o Show the status of the internal instruction queue

A
  • QS1 and QS0
61
Q
  • Ancillary component to 8086/8088 microp
A

8284A Clock Generator

62
Q
  • AEN1 and AEN2
A

o Address enable pins

63
Q

o Provided to qualify the bus ready signals

A
  • AEN1 and AEN2
64
Q
  • RDY1 and RDY2
A

o Bus ready

65
Q

o Provided, in conjunction with AEN1 and AEN2, to cause wait states

A
  • RDY1 and RDY2
66
Q
  • X1 and X2
A

o Crystal oscillator

67
Q

o Connect to an external crystal used as the timing source for the clock generator etc.

A
  • X1 and X2
68
Q
  • F/C
A

o Frequency/crystal

69
Q

o Chooses the clocking source for 8284A

A
  • F/C
70
Q
  • CLK
A

o Clock output

71
Q

o Provides the CLK input signal to the 8086/8088

A
  • CLK
72
Q
  • PCLK
A

o Peripheral clock

73
Q

o One sixth the crystal or EFI input frequency, has 50% duty cycle

A
  • PCLK
74
Q
  • OSC
A

o Oscillator output

75
Q

o TTL-level at same frequency as the crystal or EFI input

A
  • OSC
76
Q
  • RES
A

o Reset input

77
Q

o Active low input to 8284A

A
  • RES
78
Q

o Reset output is connected to the 8086/8088 RESET input pin

A
  • RESET
79
Q
  • CSYNC
A

o Clock synchronization

80
Q

o Used whenever the EFI input provides synchronization in systems with multiple processors

A
  • CSYNC
81
Q

o Connects to ground

A
  • GND
82
Q

o Connects to 5 V +-10% tolerance

A
  • VCC
83
Q

Three buses

A

o Address bus
o Data bus
o Control bus

84
Q
  • Bus cycles = ____ system-clocking periods
A

four

85
Q
  • 8086 __ data bus bits
A

16

86
Q
  • 8088 has __ data bus bits
A

8

87
Q
  • Sampled at end of T2
A

READY Input

88
Q
  • Synchronized ready input to the 8284A clock generator
A

RDY

89
Q

o Least expensive way to operate the 8086/8088 microp

A
  • Minimum mode operation
90
Q

o Some control signals must be externally generated

A
  • Maximum mode operation
91
Q

o System operated in maximum mode must have this
o Provide the signals eliminated

A
  • 8288 Bus Controller
92
Q

o Connected to the status output pins on the 8086/8088 microp

A
  • S2, S1, and S0
93
Q

o Provides internal timing

A
  • CLK
94
Q

o Demultiplex address/data

A
  • ALE
95
Q

o Controls the bidirectional data bus buffers

A
  • DEN
96
Q

o Output by the 8288 to control the direction of the bidirectional data bus buffers

A
  • DT/R
97
Q

o Causes the 8288 to enable the memory control signals

A
  • AEN
98
Q

o Enables the command output pins on the 8288

A
  • CEN
99
Q

o I/O bus mode input selects either the I/O bus mode or system bus mode operation

A
  • IOB
100
Q
  • AIOWC
A

o Advanced I/O write command

101
Q

o Used to provide I/O with an advanced I/O write control signal

A
  • AIOWC
102
Q

o I/O read command output provides I/O with its read control signal

A
  • IORC
103
Q

o I/O write command output provides I/O with its write control signal

A
  • IOWC
104
Q
  • AMWT
A

o Advanced memory write

105
Q

o Provides memory with an early or advanced write signal

A
  • AMWT
106
Q
  • MWTC
A

o Memory write control

107
Q

o Provides memory with its normal write control signal

A
  • MWTC
108
Q
  • MRDC
A

o Memory read control

109
Q

o Provides memory with its normal read control signal

A
  • MRDC
110
Q
  • INTA
A

o Interrupt acknowledge

111
Q

o Acknowledges an interrupt request input applied to the INTR pin

A
  • INTA
112
Q
  • MCE/PDEN
A

o Master cascade/peripheral data

Microprocessors (28 decks)

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