Chapter 9

Question 1

Define

Purpose of Operating System

Answer 1

To mask the details of the hardware from the programmer and provide the programmer with a convenient interface for using the system

Question 2

List

Services OS provides

Answer 2

Program creation
Program execution
Access to I/O devices
Controlled access to files
System access
Error detection and response
Accounting

Question 3

List

Key interfaces in a typical computer system

Answer 3

Instruction set architecture (ISA)
Application binary interface (ABI)
Application programming interface (API)

Question 4

Define

Instruction set architecture

Answer 4

Defines the machine language instructions that a computer can follow.
Boundary between hardware and software.

Question 5

Define

Application binary interface

Answer 5

Defines a standard for binary portability across programs.
Defines the system call interface to the operating system and the hardware resources and services available in a system through the user ISA

Question 6

Define

Application programming interface

Answer 6

Gives a program access to the hardware resources and services available in a system through the user ISA supplemented with high-level language (HLL) library calls.
Using an API enables applicatoin software to be ported easily to other systems that support the same API

Question 7

Describe

How the OS is unusual as a control mechanism

Answer 7

It functions as ordinary computer software - is a program executed by the processor.
OS frequently relinquishes control and must depend on the processor to allow it to regain control.

Question 8

List

Types of Operating systems

Answer 8

Interactive system
Batch system

Question 9

Define

Interactive system

OS type

Answer 9

The user/programmer interacts directly with the computer to request the execution of a job or to perform a transaction.
User may, depending on the nature of the application, communicate with the computer during the execution of the job

Question 10

Define

Batch system

OS type

Answer 10

Opposite of interactive. The user’s program is batched together with programs from other users and submitted by a computer operator. After the program is completed results are printed out for the user.

Question 11

Describe

Batch OS from view of processor

Answer 11

Processor executes instructions from the portion of main memory containing the monitor. These instructions are in the job control language (JCL). The monitor handles setup and scheduling

monitor = batch OS

Question 12

List

Desirable hardware features

Answer 12

Memory protection
Privileged instructions
Timer
Interrupts

Question 13

Define

Memory protection

Answer 13

User program must not alter the memory area containing the monitor.
The process hardware should detect an error and transfer control to the monitor
The monitor aborts the job, prints an error message, and loads the next job

Question 14

Define

Privledged instructions

Answer 14

Can only be executed by the monitor
If the processor encounters such an instruction while executing a user program, and error interrupt occurs.
I/O instructions are privileged so the monitor retains control of all I/O devices

Question 15

Define

Batch multiprogramming vs Time Sharing

Answer 15

BM: maximizes processor use. JCL commands provided with the job.
Time Share: minimizes response time. Commands entered at the terminal.

Question 16

Define

Long-term scheduling

Answer 16

The decision to add to the pool of processes to be executed.

Determines which programs are submitted for processing.
Once submitted, a job becomes a process for the short term scheduler.
In some systems a newly created process begins in a swapped-out condition, in which case it is added to a queue for the medium-term scheduler.

Question 17

Define

Medium-term scheduling

Answer 17

The decision to add to the number of processes that are partially or fully in mm.

Part of swapping function.
Swapping-in decision is based on the need to manage the degree of multiprogramming.
Swapping-in decision will consider the memory requirements of the swapped-out processes

Question 18

Define

Short-term scheduling

Answer 18

The decision as to which available process will be executed by the processor

AKA dispatcher
Executes frequently and makes the fine-grained decision of which job to execute next

Question 19

Define

I/O scheduling

Answer 19

The decision as to which process’s pending I/O request shall be handled by an available I/O device

Question 20

Define

Advantages and disadvantages of Demand Paging

Answer 20

Each page of a process is brought in only when it is needed
Adv: More processes can be maintained in memory. Time is saved because unused pages are not swapped in and out of memory
Dis: When one page is brought in, another must be replaced. If a page is thrown out before used, OS must get again. Thrashing

Question 21

Define

Segmentation

Answer 21

Usually visible to the programmer.
Provided as a convenience for organizing programs and data and as a means for associating privilege and protection attributes with instructions and data.
Allows the programmer to view memory as consisting of multiple address spaces or segments.

Question 22

List

Advantages of segmentation

Answer 22

• Simplifies handling of growing data structures
• Allows programs to be altered and recompiled independently without requiring that an entire set of programs be re-linked and re-loaded
• Lends itself to sharing among processes
• Lends itself to protection

Question 23

Describe

Intel x86 and Memory Mangement

for referring on test, understand more than memorize

Answer 23

Includes hardware for both segmentation and paging.
Unsegmented unpaged memory - virtual address same as physical address. Useful in low-complexity, high-performance controller applications.

Unsegmented paged memory - memory is viewed as a paged linear address space. Protection and management of memory is done via paging. Favored by some OSs

Segmented unpaged memory - Memory is viewed as a collection of logical address spaces. Affords protection down to level of single byte. Guarantees that the translation table needed is on-chip when the segment is in memory. Results in predictable access times.

Segmented paged memory - Segmentation is used to define logical memory partitions subject to access control, and paging is used to manage the allocation of memory within the partitions. Operating systems such as UNIX System V favor this view

Question 24

Describe

Segmentation bit details

Answer 24

Each virtual address consists of a 16-bit segment reference (2 bits deal with protection mech, 14 specify seg) and a 32-bit offset.

Unsegmented virtual memory is 2^32 = 4Gbytes.

Segmented virtual memory is 2^46 = 64Tbytes.

Physical address space employs a 32-bit address for a maximum of 4Gbytes.

Virtual address space is divided into two parts: global and local.

Question 25

Define

Segment Protection

Answer 25

Associated with each segment are two forms of protection: Privilege level and Access attribute.

Question 26

Define

Privilege level

Answer 26

For privilege levels, from 0 (most protected) to 3 (least protected).
Privilege level associated with data segment is “classification.”
Privilege level associated with a program segment is its “clearance.”
Privilege mechanism also limits the use of certain instructions.

Question 27

List and define

Segment descriptor

memory management parameters

Answer 27

Base - defines starting address of segment within the 4Gb linear address space.
D/B bit - indicates whether operands and addressing modes are 16 or 32 bits.
Descriptor Privilege level (DPL)
**Granularity bit (G) **- inidicates whether limit is to be interpreted in units by one byte or 4 Kbytes
**Limit **- defines size of seg, interprets based on G
S bit - Determines whether a given seg is a system, code, or data segment
**Segment Present bit (P) **- Used for nonpaged systems. Indicates if seg is present in mm. For paged, bit always set to 1
Type - distinguishes between various kinds of segments and indicates access attributes

Question 28

List and Define

Page Directory Entry and Page Table Entry

memory management parameters

Answer 28

**Accessed bit (A) **- set to 1 by processor in both levels of page tables when a r/w operation to the corresponding page occurs.
Dirty bit (D) - set to 1 by processor when a write operation to the corresponding page occurs.
Page Frame Address - Provides the physical addres of the page in memory if the present bit is set. Since page frames are aligned on 4K boundaries, the bottom 12 bits are 0, and only the top 20 bits are included in the entry. In a page directory, the address is that of a page table.
Page Cache Disable bit (PCD) - indicates whether data from page may be cached
Page size bit (PS) - indicates whether a page size is 4 Kbyte or 4 Mbyte
Page Write Through bit (PWT) - Indicates whether write-through or write-back caching policy will be used for data in the corresponding page.
**Present bit (P) **- indicates whether page table or page is in mm
R/W bit - For user-level pages, indicates whether the page is read-only access or r/w access.
**User/Supervisor bit (US) **- indicates whether page is available only to op system (sup level) or to ops and apps (user level)

Question 29

Define

Paging

Answer 29

Segmentation may be disabled, in which case linear address space is used.
Two level page lookup: first, page directory (1024 entries max, splits 4Gb linear mem into 1024 page groups of 4 Mb, each page table has 1-24 entries corresponding to 4kb pages, can use one page directory for all processes (one per process or mixture), page directory for current process always in mem)
Use TLB holding 32 page table entries
Two page sizes available, 4k or 4M

Question 30

List

Virtual memory address translation sizes

Answer 30

Supersections (optional) - consist of 16-MB blocks of main memory
Sections - consist of 1MB blocks of main memory
Large pages - consist of 64kB blocks of main memory
Small pages - consist of 4kB blocks of main memory

Sections and supersections are supported to allow mapping of a large region of memory while only using a single entry in the TLB

Question 31

Define

Virtual memory address translation tables

Answer 31

Level 1 table: Holds level 1 descriptors that contain the base address and translation properties for a Section and Supersection, and translation properties and pointers to a level 2 table for a large page or a small page.

Level 2 table: Holds level 2 descriptors that contain the base address and translation properties for a Small page or a Large page. Requires 1kB of memory

Question 32

List and define

ARM Memory-Management Parameters

don’t memorize

Answer 32

Access Permission (AP), Access Permission Extension (APX) -
control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.
Bufferable (B) bit - Determines, with the TEX bits, how the write buffer is used for cacheable memory.
Cacheable (C) bit - Determines whether this memory region can be mapped through the cache.
Domain - Collection of memory regions. Access control can be applied on the basis of domain.
not Global (nG) - Determines whether the translation should be marked as global (0), or process specific (1).
Shared (S) - Determines whether the translation is for not-shared (0), or shared (1) memory.
SBZ - Should be zero.
Type Extension (TEX) - together with the B and C bits, control accesses to the caches, how the write buffer is used, and if the memory region is shareable and therefore must be kept coherent.
Execute Never (XN)- Determines whether the region is executable (0) or not executable (1).

Question 33

Define

Access Control

Answer 33

A region of memory can be designated as no access, read only, or r/w