Chapter 8 Flashcards

Input/Output

1
Q

List and define

Three categories of External Devices

A
  • Human Readable – video display terminals, printers
  • Machine readable – mag disk and tape systems, sensors and actuators
  • Communication – for communication with remote devices such as a terminal, machine readable device, or another computer
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2
Q

List

Major functions for an I/O module

A
  • Control and timing
  • Processor communication
  • Device communication
  • Data buffering
  • Error detection
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3
Q

List

Three possible techniques for I/O operations

A

Programmed I/O
Interrupt-driven I/O
Direct memory access I/O (DMA)

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4
Q

Define

Programmed I/O

A

Data are exchanged between the processor and the I/O module.
Processor executes a program that gives it direct control of the I/O operation.
When the processor issues a command it must wait for the I/O operation to complete.
If the processor is faster than the I/O module, this is wasteful of processor time

Transfer through processor, does not use interrupts

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5
Q

Define

Interrupt-driven I/O

A

Processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the latter has completed its work.

Transfer through processor, uses interrupts

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6
Q

Define

Direct memory access (DMA)

A

The I/O module and mm exchange data directly without processor involvement. Most efficient method for moving large volumes of data.

Transfer straight to main memory, uses interrupts

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7
Q

Describe

Drawbacks of Programmed and Interrupt-drive I/O

A
  1. The I/O transfer rate is limited by the speed with which the processor can test and service a device.
  2. The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer
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8
Q

List and define

Four types of I/O commands

A
  1. Control – used to activate peripheral and tell it what to do
  2. Test – tests status conditions of I/O and peripherals
  3. Read – obtains data from peripheral and places in internal buffer
  4. Write – causes I/O module to take data from data bus and transmit to peripheral
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9
Q

Define

I/O mapping summary

two types

A

Memory mapped I/O – devices and memory share an address space. I/O looks just like r/w, no special commands.

Isolated I/O – separate address spaces. Needs I/O or memory select lines. Special commands (limited set)

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10
Q

Describe

Two design issues with implementing interrupt I/O

A
  • Because there will be multiple I/O modules, how does the processor determine which device issued the interrupt?
  • If multiple interrupts have occured, how does the processor decide which one to process?
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11
Q

List

4 general categories of techniques to identify which device interrupted

A
  • Multiple interrupt lines
  • Software poll
  • Daisy chain (hardware poll, vectored)
  • Bus arbitration (vectored)
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12
Q

Define

Multiple interrupt lines

A

Between the processor and I/O modules. Most straightforward approach. Even if multiple lines are used, likely that each line will have multiple I/O modules attached to it.

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13
Q

Define

Software poll

A

When the processor detects and interrupt it branches to an interrupt service routine whose job is to poll each I/O module to determine which module caused the interrupt. Time consuming.

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14
Q

Define

Daisy chain

interrupts

A

The interrupt acknowledge line is daisy chained through the modules. Vector -address of the I/O module or some other unique identifier. Vector interrupt - processor uses the vector as a pointer to the appropriate device service routine, avoiding the need to execute a general interrupt service routine first.

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15
Q

Define

Bus arbitration

A

An I/O module must first gain control of the bus before it can raise the interrupt request line. When the processor detects the interrupt it responds on the interrupt acknowledge line. Then the requesting module places its vector on the data lines.

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16
Q

Descibe

Process of transmitting data in DMA scheme

A

Application that wants to transmit data places it in an assigned buffer in main memory.
The core transfers this to a system buffer in main memory and creates necessary TCP and IP headers, which are also buffered in system memory.
The packet is then picked up via the DMA for transfer via the NIC.
This activity engages not only main memory but also the cache.
Similar transfers between system and app buffers are required for incoming traffic

17
Q

Define

Direct cache access: simplest strategy

A

This form of DCA applies only to incoming network traffic. The DCA function in the memory controller sends a prefetch hint to the core as soon as the data is available in system memory. This enables the core to prefetch the data packet from the system buffer.

18
Q

Describe

Direct cache access: Direct data I/O

A

The packet and packet descriptor information are accessed only once in the system buffer by the core. For incoming packets, the core reads the data from the buffer and transfers the packet payload to an application buffer. It has no need to access the data in the system buffer again.

Cache injection

19
Q

List

Evolution of the I/O function

A
  1. CPU directly controls a peripheral device
  2. A controller or I/O module is added. CPU uses programmed I/O without interrupts
  3. Same configuration as 2, but with interrupts.
  4. I/O module given direct memory access via DMA, only needs CPU at beginning and end of transfer
  5. I/O module is enhanced to become processor in own right
  6. I/O module has local memory of own and is computer in its own right. Large set of I/O devices can be controlled with minimal CPU involvement
20
Q

Define

Universal Serial Bus

A

(USB) Widely used for peripheral connections, default for slower speed devices. Commonly used high-speed I/O. Is controlled by root host controller which attaches to devices to create a local network with a heirarchical tree topology

21
Q

Define

Small computer system interface

A

Old standard for connecting peripheral devices to small and medium sized computers. Physical organiation is shared bus that can support 16 or 32 devices, depending on generation. Speed ranges from 5 Mbps to 160 Mbps

22
Q

Define

FireWire Serial Bus

A

Uses daisy chain configuration, up to 63 devices connected off single port. Provides for hot plugging which makes it possible to connect and disconnect
peripherals without having to power the computer system down or reconfigure the system. Provides for automatic configuration. No terminations and the system automatically performs a configuration function to assign addresses

23
Q

Define

Thunderbolt

A

Most recent and fastest peripheral connection technology to become available for general-purpose use. Developed by Intel with collaboration from Apple. The technology combines data, video, audio, and power into a
single high-speed connection for peripherals such as hard drives, RAID arrays, video-capture boxes, and network interfaces. Provides up to 10 Gbps throughput in each direction and up to 10 Watts of power to connected peripherals

24
Q

Define

SATA

A

Serial Advanced Technology
Attachment. An interface for disk storage systems.
Provides data rates of up to 6 Gbps, with a maximum per device of 300 Mbps.
Widely used in desktop computers and in industrial and embedded applications

25
Q

Define

InfiniBand

A

I/O specification aimed at the high-end server market
* First version was released in early 2001
* Heavily relied on by IBM zEnterprise series of mainframes
* Standard describes an architecture and specifications for data flow among processors and intelligent I/O devices
* Has become a popular interface for storage area networking and other large storage configurations
* Enables servers, remote storage, and other network devices to be attached in a central fabric of switches and links
* The switch-based architecture can connect up to 64,000 servers, storage systems, and networking devices