Chapter 3

Question 1

List

The three concepts von Neumann architecture is based on

Answer 1

1. Data and instructions stored in a single read-write memory
2. Contents of this memory are addressable by location, without regard to the type of data contained there
3. Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next

Question 2

Define

Hardwired Program

Answer 2

The results of the process of connecting various components in the desired configuration

Question 3

Define

Difference between hardware and software programming

Answer 3

Software doesn’t have to be rewired for each new program. Requires Instruction interpreter into general purpose functions.

Question 4

Define

I/O Address Registrar (I/OAR)

Answer 4

Specifies a particular I/O device

Question 5

Define

I/O Buffer Registar (I/OBR)

Answer 5

Used for the exchange of data btwn an I/O module and the CPU

Question 6

Describe

Fetch Cycle

Answer 6

First: processor fetches instruction from memory.
Next: PC holds address of instruction next fetched (incremented after each fetch)
Then: fetched instruction loaded into IR
Finally: processor interprets and performs required action

Question 7

List

Classes of Interrupts

Answer 7

Program
Timer
I/O
Hardware failure

Question 8

Define

Function of I/O

Answer 8

Can exchange data directly with processor, or do direct memory access (DMA) if processor allows (this frees processor)

Question 9

Define

Bus interconnection

Answer 9

Usually consists of multiple communication lines, each line capable of transmitting signals representing binary 1 and 0

Question 10

Define

System bus

Answer 10

Connects major components

Question 11

Define

Data bus

Answer 11

Moves data on data lines; 32, 64, or 128 separate lines. Number of lines == width of bus

Question 12

Define

Address bus

Answer 12

Used to designate the source or destination of data. Separate from data lines. Width determines max possible memory capacity of system

Question 13

Define

Control bus

Answer 13

Controls access, timing info, because a bus is shared by all the components it goes to.

Question 14

Define

Quick Path Interconnect (QPI)

Answer 14

Uses Point-to-point interconnection, multiple direct pairwise connections, layered architecture, packetized data transfer.

Question 15

List

QPI packet layers

Answer 15

Protocol
Routing
Link
Physical

Question 16

Define

QPI Link Layer

Answer 16

Two key functions: flow control and error control. Packets called Flits (flow control units). Each flit contains 72 bit payload and 8 bit CRC

Question 17

Define

Flow Control

Of QPI Link Layer

Answer 17

Needed to ensure a sending QPI doesn’t overwhelm a receiving QPI

Question 18

Define

Error Control Function

QPI Link Layer

Answer 18

Detects and recovers from bit errors

Question 19

Define

QPI Routing Layer

Answer 19

Determines course, defined by firmware

Question 20

Define

QPI Protocol Layer

Answer 20

Cache coherency protocol, makes sure all levels with same address have same data; sent to or from cache

Question 21

Define

Peripheral Component Interconnection (PCI)

Answer 21

A popular high bandwidth, processor independent bus that can function as a mezzanine or a peripheral bus

Mezzanine =connecting two or more parallel printed circuit boards in a stacking configuration

Question 22

Define

PCIe (express)

Answer 22

Point-to-point interconnection scheme intended to replace bus. Required to support Gigabit Ethernet

Question 23

List

PCIe Layers

Answer 23

Transaction
Data Link
Physical

Question 24

Define

PCIe Transaction Layer

Answer 24

Receives read and write requests from software above and creates request packets. Supports four address spaces: memory, I/O, Configuration, and Message.