Chapter 6

Question 1

List

The two technologies that RAM technology is divided into

Answer 1

Dynamic RAM
Static RAM

Question 2

Define

DRAM

Answer 2

Made with cells that store data as charge on capacitors.
Presence or absence of charge interpreted as 1 or 0.
Requires periodic charge refreshing to maintain data storage.
The term dynamic refers to tendency of stored charge to leak away, even with power continuosly applied.

dynamic RAM

considered analog

Question 3

Define

SRAM

Answer 3

Digital device that uses the same logic elements used in the processor.
Binary values are stored using traditional flip-flop logic gate configurations.
Will hold data as long as power is supplied to it.

static RAM

Considered Digital

Question 4

Define

SRAM vs. DRAM

Answer 4

both volatile
DRAM: simpler to build, smaller, more dense, less expensive, requires the supporting refresh circuitry, tend to be favored for large memory requirements, used for main memory.

SRAM: faster, used for cache memory (both on and off chip)

Question 5

Define

Read Only Memory (ROM)

Answer 5

Contains a permanent pattern of data that cannot be changed or added to.
No power source required (non-volatile)
Data or program is permanent in main memory and never needs to be loaded from a secondary storage device.
Data is actually wired into the chip as part of the fabrication process.

Question 6

Define

Disadvantages of ROM

Answer 6

No room for error, if 1 bit is wrong, the whole batch of ROMs must be thrown out.
Data insertion step includes a relatively large fixed cost.

Question 7

Define

Programmable ROM (PROM)

Answer 7

Less expensive alternative to ROM.
Nonvolatile and may be written into only once.
Writing process is performed electrically and may be performed by supplier or customer at a later time than the original chip fabrication.
Special equipment is required for the writing process.
Provides flexibility and convenience.
Attractive for high volume production runs.

Question 8

Define

Erasable PROM (EPROM)

programmable ROM

Answer 8

Erasure process can be performed repeatedly.
More expensive than PROM

Question 9

Define

Electrically EPROM (EEPROM)

erasable programmable ROM

Answer 9

Can be written into at any time without erasing prior contents.
Combines the advantages of non-volatility with the flexability of being updateable in place.
More expensive than EPROM.

Question 10

Define

Flash memory

Answer 10

Intermediate between EPROM and EEPROM in both cost and functionality.
Uses an electrical erasing technique that does not provide byte level erasure.
Microchip is organized so a section of memory cells are erased in a single action or a “flash.”

Question 11

Define

Interleaved memory

Answer 11

Composed of collection of DRAM chips grouped together to form a memory bank.
Each bank is independently able to service a memory read or write request.
K banks can service K requests simultaneously, increasing memory read/write by a factor of K.
If consecutive words in m are stored in different banks, the transition of a block of m is sped up.

Question 12

list

Different memory errors to correct

Answer 12

Hard failure
Soft failure

Question 13

Define

Hard failure

memory

Answer 13

Permanent or physical defect.
M cells or cells affected can’t reliably store data but become stuck at 0 or 1 or switch erratically.
Can be caused by: harsh environmental abuse, manufacturing defects, wear.

Question 14

Define

Soft error

memory

Answer 14

Random, non-destructive event that alters the contents of 1 or more memory cells.
No permanent damage to memory.
Can be caused by: power supply problems, alpha particles.

Question 15

Define need for

Advanced DRAM organization

Answer 15

One of the most critical system bottlenecks when using high-performance processors is the interface to main internal memory.
The traditional DRAM chip is constrained both by its internal architecture and by its interface to the processor’s memory bus.
A number of enhancements to the basic DRAM have been explored. Current market dominators are SDRAM and DDR_DRAM.

Question 16

Define

Synchronous DRAM (SDRAM)

Answer 16

Exchanges data with the processor synched to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.
With synchronous access the DRAM moves data in and out under control of the system clock.
The processor or other master issues the instruction and address info which is latched by the DRAM.
The DRAM then responds after a set number of clock cycles.
Meanwhile, the master can safely do other tasks while the DRAM is processing.

Question 17

Define

Double Data Rate SDRAM (DDR SDRAM)

Answer 17

Developed by the JEDEC.
Numerous companies make DDR chips.
Achieves higher data rates in three ways:
1. data transfer is synched to both the rising and falling edge of the clock, rather than just the rising edge.
2. DDR uses higher clock rate on the bus to increase the transfer rate
3. A buffering scheme is used.

Question 18

Define

JEDEC Solid State Technology Organization

Answer 18

Electronic Industry Alliance’s semiconductor engineering standardization body

Question 19

Define

Embedded DRAM (eDRAM)

Answer 19

A DRAM integrated on the same chip as or MCM of an app-specific integrated circuit (ASIC) or microprocessor.
For a number of metrics, eDRAM is intermediate between on-chip SRAM and offchip DRAM.
Better than SRAM in memory size, and cost-per-bit, but DRAM still better.
Worse than SRAM in access time, but better than DRAM.

Question 20

Define

How flash memory works

Answer 20

Starts with typical transistor and adds a second gate called floating gate. Initially the floating gate doesn’t interfere, this state represents 1. But applying a large voltage across the oxidizing layer that makes it ‘floating’ causes electrons to tunnel through it and become trapped, even if power is disconnected. This represents 0. Large voltage from the opposite direction returns state to 1.

Question 21

Define

NOR flash memory

Answer 21

Basic access unit is a bit, referred to as a memory cell. Cells are connected in parallel to the bit lines so each cell can be read/write/erased individually. If any memory cell of the device is turned on by the corresponding word line, the bit line goes low.

Traditionally preferred for internal memory

Question 22

Define

NAND flash memory

Answer 22

Organized in transistor arrays with 16 or 32 transistors in series. The bit line goes low only if all the transistors in the correspnding word lines are turned on.

Traditionally preferred for external memory

Question 23

List

New memory technologies coming soon

Answer 23

STT-RAM
PCRAM
ReRAM

Question 24

Define

STT-RAM

Answer 24

Spin-transfer torque RAM.
New type of magnetic RAM (MRAM).
Employs new write method called polarization-current-induced magnetic switching.
Features non-volatility, fast r/w speed, high program endurance, and zero standby power.

good candidate for cache or main memory

Question 25

Define

PCRAM

Answer 25

Phase-changing.
Something with chalcogenide-based material.

good candidate to replace or supplement DRAM for main memory

Question 25

Define

ReRAM

aka RRAM

Answer 25

Resistive RAM.
Creates resistance rather than directly storing charge.

Good candidate to replace or supplement secondary storage and main memory