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Computer Architecture > Chapter 1 > Flashcards

Chapter 1 Flashcards

Basic Concepts and Computer Evolution

1
Q

Define

Computer Architecture

A

Attributes of a system visible to the programmer and have a direct impact on logical execution of a program.

I/O mechanisms

Architectural decision whether comp will have multiply instruction

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2
Q

Define

Computer organization

A

The operational units and their interconnections that realize the architectural specifications. Includes hardware details transparent to programmer.

Control signals, interfaces between computer and peripherals , memory technology used. Decides how instructions will be implemented

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3
Q

List

4 basic functions computer can perform

A

Data processing
Data storage
Data movement
Control

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4
Q

List

4 main structural components of computer

A

CPU
Main memory
I/O
System interconnection

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5
Q

List

Major structural components of CPU

A

Control Unit
Arithmetic and logic unit
Registers
CPU Interconnection

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6
Q

Definition of Registers

A

Provides storage internal to the CPU

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7
Q

List

Multicore Computer Structure

A

CPU
Core
Processor

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8
Q

Definition of Core

A

An individual processing unit on a processor chip; may be equivalent in functionality to CPU on a single-CPU system.

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9
Q

Definition of Processor

A

A physical piece of silicon containing one or more cores. Is the computer component that interprets and executes instructions

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10
Q

Define

Cache memory

A

Multiple layers of memory between the processor and main memory. Greater performance increase if use multiple levels, with level 1 closest to the core and level (n) furthest.

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11
Q

Define

Memory Buffer Register (MBR)

A

Contains a word to be stored in memory or sent to I/O unit, or is used to receive a word from memory or I/O.

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12
Q

Define

Memory Address Register (MAR)

A

Specifies the address in memory of the word to be written from or read into the MBR.

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13
Q

Definition of Word

A

A unit of data of a defined bit length that can be addressed and moved between storage and the computer processor.

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14
Q

Define

Instruction Register (IR)

A

Contains the 8-bit opcode instruction bit being executed.

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15
Q

Define

Instruction Buffer Register (IBR)

A

Employed to temporarily hold the right-hand instruction from a word in memory.

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16
Q

Definition

Program Counter (PC)

A

Contains the address of the next instruction pair to be fetched from memory.

17
Q

Define

Accumulator (AC) and Multiplier Quotient (MQ)

A

Employed to temporarily hold operands and results of ALU operations.

18
Q

Gate

A

Device that implements a single boolean logic function.

19
Q

Memory Cell

A

Device that can store one bit of data; that is, can be in one stable state at a time.

20
Q

4 basic functions of computer related to gates and memory cells

A

Data storage provided by memory cells

Data processing provided by gates

Data movement is the paths among components that are used to move data from memory to memory and from memory through gates to memory

Control: the paths can carry control signals

21
Q

Transistors

A

The fundamental building block of digital circuits, used to construct processors, memory cells, and other digital logic devices

22
Q

Moore’s Law

A

Number of transistors that can be put on a single chip was doubling every year.

23
Q

Embedded Systems

A

The use of electronics software within a product.

24
Q

The 2 general approaches for developing an embedded OS

A
  1. Take existing OS and adapt it for the embedded application.
  2. Design and implement an OS intended solely for embedded use.
25
Q

Define

Application processors

A

Defined by processor’s ability to execute complex OS’s. General-purpose in nature, like the smartphone.

26
Q

Define

Dedicated processors

A

Dedicated to one or a small number of specific tasks required by host device. Reduced size and cost.

27
Q

Deeply Embedded Systems

A

Dedicated, single-purpose devices that detect something in the environment, perform a basic level of processing, and do something with the results.

28
Q

ARM

A

Process architecture evolved from RISC design principles and is used in embedded systems. Advanced RISC Machine.

29
Q

RISC

A

Reduced Instruction Set Computer

30
Q

Define

ISU (Instruction Sequence Unit)

Part of internal structure of single core

A

Determines the sequence in which instructions are executed in superscaler architecture. Tracks register names, out-of-order instruction dependency, and handling of instruction resource dispatch

Part of internal structure of single core

31
Q

Define

IFB (instruction fetch and branch) and ICM (instruction cache and merge)

Part of internal structure of single core

A

Contain 128kb instruction cache, branch prediction logic, instruction fetch controls, and buffers.

Part of internal structure of single core

32
Q

Define

IDU (instruction decode unit)

Part of internal structure of single core

A

Fed from the IFU buffers, and is responsible for the parsing and decoding of all z/ Architecture operation codes.

Part of internal structure of single core

33
Q

Define

LSU (load-store unit)

Part of internal structure of single core

A

Contains 96kb L1 data cache, manages data traffic btwn L2 data cache and the functional execution units. Responsible for handling all types of operand access of all lengths, modes, and formats

34
Q

Define

XU (translation unit)

Part of internal structure of single core

A

Translates logical addresses from instructions into physical address in main memory. Also contains a translation lookaside buffer (TLB) used to speed up memory access.

Part of internal structure of single core

35
Q

Define

PC (core pervasive unit)

Part of internal structure of single core

A

Used for instrumentation and error collection

Part of internal structure of single core

36
Q

Define

FXU (fixed-point unit)

Part of internal structure of single core

A

Executes fixed-point arithmetic operations

Part of internal structure of single core

37
Q

Define

VFU (vector and floating-point units)

Part of internal structure of single core

A

Handles binary, hex, and decimal floats and operations performed on them. Also handles vector operations.

Part of internal structure of single core

38
Q

Define

RU (recovery unit)

Part of internal structure of single core

A

Keeps a copy of complete state of system that includes all registers, collects hardware fault signals, and manages hardware recovery actions.

Part of internal structure of single core

39
Q

Define

COP (dedicated co-processor)

Part of internal structure of single core

A

Responsible for data compression and encryption functions for each core

Part of internal structure of single core

Computer Architecture (11 decks)

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