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Computer Science > Chapter 3.1 (A) CPU, Architecture, Cache/Cores > Flashcards

Chapter 3.1 (A) CPU, Architecture, Cache/Cores Flashcards

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1
Q

What does CPU stand for

A

Central Processing Unit

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2
Q

What components does the CPU consist of

A

Control Unit (CU)
Arithmetic and logic unit (ALU)
Registers
Busses

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3
Q

What does the CPU do

A

execution or processing of all the instructions and data in a computer

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4
Q

What is the Von Neumann architecture

A

A type of computer architecture which introduced the concept of stored programs in 1940s

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5
Q

What is an ALU

A

The component of the CPU that carries out all arithmetic and logical operations

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6
Q

Examples of arithmetic operations that are carried out by ALU

A

+, -, logical shifting ( multiplication and division)

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7
Q

Examples of LOGIC operations that are carried out by ALU

A

AND and OR

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8
Q

What is a register

A

A temporary component in the CPU which can be
general or specific in its use; it holds data or instructions as part of the Fetch–Decode–Execute cycle

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9
Q

Types of special purpose registers

A

Current Instruction register - CIR
Accumulator - ACC
Memory Address Register - MAR
Memory Data Register - MDR
Program counter - PC

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10
Q

What is an ACC (register)

A

Accumulator - Temporary stores the results of the calculation from the ALU

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11
Q

What is a PC (register)

A

Program Counter - This register stores the address where the next instruction to be read can be found

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12
Q

What is the MAR

A

Memory Address Register - Stores the address of the memory location currently being read from or written to

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13
Q

What is the MDR

A

Memory Data Register - Stores data which has just been read from memory or data which is about to be written to memory

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14
Q

What is the CIR

A

Current information register - this register stores the current instruction being decoded and executed

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15
Q

How does the MDR differ from the MAR

A

The MAR stores the location of the data/instruction

The MDR actually holds the data/instruction itself.

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16
Q

Flow of registers

A

PC –> MAR –> MDR

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17
Q

What is the Control unit

what does it decode

A

CU - Sends control signals that manage the transfer of data and instructions within the CPU. Decodes an instruction using an instruction set

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18
Q

What is a bus
what does each wire do

A

Busses are used in computers as parallel transmission components; each wire in the bus transmits one bit of data

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19
Q

3 main types of busses

A

Address
Control
Data

20
Q

Which busses have two way flow

A

Control
Data

21
Q

What does the address bus do
direction

A

Carries addresses throughout the computer system

Unidirectional between CPU and memory

22
Q

How does width of a bus affect the bus (address)

A

Wider the bus the more memory locations can be directly addressed at any given time.

23
Q

What is a memory location

A

a numbered place in memory where values can be stored

24
Q

What is an address

A

a label for a memory location used by the CPU to track data

25
Q

What is a data bus

A

the system bus that allows data to be carried from CPU to memory (and vice versa) or to and from input/output devices

26
Q

What is a word

A

a group of bits used by a computer to represent a
single unit

27
Q

How does width affect data bus

A

Wider the bus, the larger word can be transported

28
Q

What is the control bus

A

the system bus that carries signals from control unit to all other computer components

29
Q

What is the FDE

A

Fetch-decode-execute cycle - a cycle in which instructions and data are fetched from memory, decoded and finally executed

30
Q

What happens in the fetch stage

A

Next instruction is fetched from the memory
address stored in the MAR and the instructions which are stored at that address are then temporarily stored in the MDR.

Then the contents of MDR are copied to CIR.

Finally PC is incremented by 1 so that next instruction can be processed

31
Q

What is the decode stage

A

Instruction is decoded so it can be interpreted in the next part of the cycle

32
Q

What is the execute stage

A

Instruction carried out in a logical sequence since the CPU passes the decoded instructions as a set of control signals to the appropriate components within the computer system.

33
Q

What is the system clock

A

produces timing signals on the control bus to ensure synchronisation takes place

34
Q

What is the clock cycle

A

vibrational frequency of the system clock which sends out pulses along the control bus

35
Q

How is clock cycle measured

A

Gigahertz GHz

36
Q

What is overclocking

A

changing the clock speed of a system clock to a value higher than the factory/recommended setting

37
Q

What is the BIOS

A

Basic Input/Output system - suite of programs on firmware that are used to initialize a computer system during the boot up process.

38
Q

What is cache memory

A

Temporary memory hold instructions that are freq repeated.

39
Q

Examples of backing store memory

A

HDD
SSD

40
Q

What is a core

A

a unit on a CPU made up of an ALU, control unit and registers

41
Q

Names and number of cores of CPUs

A

Dual core - 2 cores
Quad core - 4 cores

42
Q

How to increase the speed and performance of a computer

A

Increasing the bus width (data and address)

Increasing the clock speed

The use of cache memory

Use of multicore CPUs

43
Q

Problems with overclocking

A

unsynchronised operations which would lead to frequent crashes and the computer becoming unstable

Serious overheating of the CPU - unreliable performance

44
Q

Why does increasing the number of cores not always lead to an increase in performance

A

The CPU needs to communicate with a larger number of cores which could reduce overall performance

45
Q

Explain concept of stored programs

A

Data and instructions are stored in the same memory
and can only be fetched one at a time

46
Q

Purpose of 1 core

A

to process an instruction
to carry out a fetch-execute cycle

47
Q

How can upgrade to dual core impact comp from single core

A

It can now process two instructions simultaneously (where suitable)
* … increasing the performance.

Computer Science (28 decks)

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