Chapter 3: ISA & Intro to Assembly Flashcards
For a stored program computer, the CPU…
reads instructions from memory and executes them
For a stored program computer, temporary data is stored…
in registers
For a stored program computer, the PC
(Program Counter) is a register that points at the next instruction (inside the memory) to be executed
For a stored program computer, the CCR
(Condition Code Register) contains the flag bits for the processor
Computers can execute instructions ranging from
8-bits wide to multi-bytes wide
The instruction format defines the anatomy of an instruction:
- Number of operands
- Number of bits devoted to defining each operation
- Format of each operation
The PC is
(Program Counter) points to the next instruction and is incremented after each execution
The stored-program computer operates in a
fetch/execute two-phase mode
In the stored-program computer’s fetch mode:
the next instruction is read from memory AND decoded
In the stored-program computer’s execute mode:
the instruction is interpreted and executed according to the CPU’s logic
What is pipelining?
When fetch and execute operations overlap
What are the features of a stored program computer?
- Register file (r0-ri)
- PC (Program Counter)
- IR (Instruction Register)
- MAR ( Memory Address Register)
- MBR (Memory Buffer Register)
What is the Register File?
(r0-ri) is a set of general-purpose registers that store temporary working data
A computer requires at least one ______ register
General purpose
What is the PC
(Program Counter) contains the address of the next instruction to be executed. I.e points to the location in memory containing the next instruction
What is the IR
(Instruction Register) holds the instruction most recently read from memory (the instruction currently being executed)
What is the MAR
(Memory Address Register) stores the address of the location in main memory that is currently being accessed by either a read or write operation
What is the MBR
(Memory Buffer Register) stores the data that has just been read from main memory OR data that is to be written to main memory
In the fetch-phase, the PC…
(Program Counter) supplies the address of the next instruction to be executed to the MAR (Memory Address Register) and is incremented by the size of an instruction
In the fetch-phase, the MAR…
(Memory Address Register) reads the instruction which will be sent to the MBR
In the fetch-phase, the MBR…
Receives the instruction pointed at by the MAR and sends it to the IR
In the fetch-phase, the IR…
Receives the instruction from the MBR and decodes it
In the execute-phase, operands may be…
read from the register file or transferred to the ALU (Arithmetic Logic Unit) where they are operated on
In the execute-phase, if the operation requires memory access, the address is read from the …
IR
In the execute-phase, if the operation requires memory access, the address is sent to the…
MAR
In the execute-phase, if the operation requires memory access, the contents of the memory address are placed in the…
MBR
In the execute-phase, if the operation requires memory access, the contents of the MBR are finally placed in the…
Register
With constants, the IR (Instruction Register) paths the literal operand to either the…
Register file, the ALU, or the MBR
Flow control is
action that modifies the normal instruction sequence
Conditional behavior allows
the processor (based on the CCR flags) to select one of two courses of action:
- Continue executing the next instruction in sequence
- Load the PC with a new value and executing a branch of another region of code
The root of flow control is
The ALU which determines the flags of the CCR
The CCR is determined by the
ALU
The four status flags are:
Zero (Z) flag if the result is zero
Negative (N) flag (in two’s complement) if the result is negative
Carry (C) flag if the result generated a carry-out
oVerflow (V) flag if the result generated arithmetic overflow
In terms of status flags, the difference between CISC and RISC is
CISC (Complex Instruction Set Computer) automatically sets the status flags after each operation
RISC (Reduced Instruction Set Computer) requires the programmer to request to update the flags
In ARM, general purpose registers can be used for
Anything
In ARM, there are __ specific purpose registers
2
Registers in arm are how many bits wide?
32 (4 bytes)
What are the two addressing modes supported by ARM?
Literal/immediate and register-indirect/pointer-based/indexed
What addressing mode is not supported by ARM?
Direct/absolute
What is Literal/immediate addressing?
the actual value is part of the instruction
What is direct/absolute addressing?
the instruction contains the memory address of the instruction
What is register-indirect/pointer-based/indexed addressing?
the register contains the address of the operand
What are the three types of instructions?
Memory-to-register
Register-to-memory
Register-to-register
What instruction type is supported by ARM?
Register-to-register
LDR and STR are special forms of what?
pseudo-instructions
In terms of the amount of addresses that can be stored in an instruction, CISC has ___ and RISC has ___ typically
CISC: 2
RISC: 3
RISC typically has ___ address instructions where they are all ___
3 address instructions which are all registers
Does RISC support 3 memory address instructions?
NO
Does RISC support 3 register instructions?
Yes
What does ARM stand for?
Advanced RISC Machines
In ARM, a half-word is ____ bits and a full word is ____ bits
A half word is 2 bytes (16 bits)
A full word is 4 bytes (32 bits)
ARM’s register set has ___ registers
16 registers
ARM’s general purpose registers are:
r0 - r12
ARM’s PC register is r__
r15
ARM’s CPSR stands for
Current Program Status Register
ARM’s CPSR contains flag bits at what indexes?
28, 29, 30, 31
What are the two types of ARM statements?
Executable instructions
Assembler directives
Assembler directives are:
Statements that tell the assembler something about the environment
Executable Instructions are…
Statements that are executed by the computer
Lines to be executed by the computer are called
Executable Instructions
Lines that tell the assembler something about the environment are called
Assembler Directives
