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CS2208 > Chapter 3: ISA & Intro to Assembly > Flashcards

Chapter 3: ISA & Intro to Assembly Flashcards

1
Q

For a stored program computer, the CPU…

A

reads instructions from memory and executes them

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2
Q

For a stored program computer, temporary data is stored…

A

in registers

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3
Q

For a stored program computer, the PC

A

(Program Counter) is a register that points at the next instruction (inside the memory) to be executed

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4
Q

For a stored program computer, the CCR

A

(Condition Code Register) contains the flag bits for the processor

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5
Q

Computers can execute instructions ranging from

A

8-bits wide to multi-bytes wide

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6
Q

The instruction format defines the anatomy of an instruction:

A
  • Number of operands
  • Number of bits devoted to defining each operation
  • Format of each operation
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7
Q

The PC is

A

(Program Counter) points to the next instruction and is incremented after each execution

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8
Q

The stored-program computer operates in a

A

fetch/execute two-phase mode

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9
Q

In the stored-program computer’s fetch mode:

A

the next instruction is read from memory AND decoded

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10
Q

In the stored-program computer’s execute mode:

A

the instruction is interpreted and executed according to the CPU’s logic

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11
Q

What is pipelining?

A

When fetch and execute operations overlap

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12
Q

What are the features of a stored program computer?

A
  • Register file (r0-ri)
  • PC (Program Counter)
  • IR (Instruction Register)
  • MAR ( Memory Address Register)
  • MBR (Memory Buffer Register)
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13
Q

What is the Register File?

A

(r0-ri) is a set of general-purpose registers that store temporary working data

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14
Q

A computer requires at least one ______ register

A

General purpose

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15
Q

What is the PC

A

(Program Counter) contains the address of the next instruction to be executed. I.e points to the location in memory containing the next instruction

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16
Q

What is the IR

A

(Instruction Register) holds the instruction most recently read from memory (the instruction currently being executed)

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17
Q

What is the MAR

A

(Memory Address Register) stores the address of the location in main memory that is currently being accessed by either a read or write operation

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18
Q

What is the MBR

A

(Memory Buffer Register) stores the data that has just been read from main memory OR data that is to be written to main memory

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19
Q

In the fetch-phase, the PC…

A

(Program Counter) supplies the address of the next instruction to be executed to the MAR (Memory Address Register) and is incremented by the size of an instruction

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20
Q

In the fetch-phase, the MAR…

A

(Memory Address Register) reads the instruction which will be sent to the MBR

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21
Q

In the fetch-phase, the MBR…

A

Receives the instruction pointed at by the MAR and sends it to the IR

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22
Q

In the fetch-phase, the IR…

A

Receives the instruction from the MBR and decodes it

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23
Q

In the execute-phase, operands may be…

A

read from the register file or transferred to the ALU (Arithmetic Logic Unit) where they are operated on

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24
Q

In the execute-phase, if the operation requires memory access, the address is read from the …

A

IR

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25
Q

In the execute-phase, if the operation requires memory access, the address is sent to the…

A

MAR

26
Q

In the execute-phase, if the operation requires memory access, the contents of the memory address are placed in the…

A

MBR

27
Q

In the execute-phase, if the operation requires memory access, the contents of the MBR are finally placed in the…

A

Register

28
Q

With constants, the IR (Instruction Register) paths the literal operand to either the…

A

Register file, the ALU, or the MBR

29
Q

Flow control is

A

action that modifies the normal instruction sequence

30
Q

Conditional behavior allows

A

the processor (based on the CCR flags) to select one of two courses of action:

  • Continue executing the next instruction in sequence
  • Load the PC with a new value and executing a branch of another region of code
31
Q

The root of flow control is

A

The ALU which determines the flags of the CCR

32
Q

The CCR is determined by the

A

ALU

33
Q

The four status flags are:

A

Zero (Z) flag if the result is zero

Negative (N) flag (in two’s complement) if the result is negative

Carry (C) flag if the result generated a carry-out

oVerflow (V) flag if the result generated arithmetic overflow

34
Q

In terms of status flags, the difference between CISC and RISC is

A

CISC (Complex Instruction Set Computer) automatically sets the status flags after each operation

RISC (Reduced Instruction Set Computer) requires the programmer to request to update the flags

35
Q

In ARM, general purpose registers can be used for

A

Anything

36
Q

In ARM, there are __ specific purpose registers

A

2

37
Q

Registers in arm are how many bits wide?

A

32 (4 bytes)

38
Q

What are the two addressing modes supported by ARM?

A

Literal/immediate and register-indirect/pointer-based/indexed

39
Q

What addressing mode is not supported by ARM?

A

Direct/absolute

40
Q

What is Literal/immediate addressing?

A

the actual value is part of the instruction

41
Q

What is direct/absolute addressing?

A

the instruction contains the memory address of the instruction

42
Q

What is register-indirect/pointer-based/indexed addressing?

A

the register contains the address of the operand

43
Q

What are the three types of instructions?

A

Memory-to-register

Register-to-memory

Register-to-register

44
Q

What instruction type is supported by ARM?

A

Register-to-register

45
Q

LDR and STR are special forms of what?

A

pseudo-instructions

46
Q

In terms of the amount of addresses that can be stored in an instruction, CISC has ___ and RISC has ___ typically

A

CISC: 2

RISC: 3

47
Q

RISC typically has ___ address instructions where they are all ___

A

3 address instructions which are all registers

48
Q

Does RISC support 3 memory address instructions?

A

NO

49
Q

Does RISC support 3 register instructions?

A

Yes

50
Q

What does ARM stand for?

A

Advanced RISC Machines

51
Q

In ARM, a half-word is ____ bits and a full word is ____ bits

A

A half word is 2 bytes (16 bits)

A full word is 4 bytes (32 bits)

52
Q

ARM’s register set has ___ registers

A

16 registers

53
Q

ARM’s general purpose registers are:

A

r0 - r12

54
Q

ARM’s PC register is r__

A

r15

55
Q

ARM’s CPSR stands for

A

Current Program Status Register

56
Q

ARM’s CPSR contains flag bits at what indexes?

A

28, 29, 30, 31

57
Q

What are the two types of ARM statements?

A

Executable instructions

Assembler directives

58
Q

Assembler directives are:

A

Statements that tell the assembler something about the environment

59
Q

Executable Instructions are…

A

Statements that are executed by the computer

60
Q

Lines to be executed by the computer are called

A

Executable Instructions

61
Q

Lines that tell the assembler something about the environment are called

A

Assembler Directives

CS2208 (12 decks)

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