Chapter 3: Extra Stuff

Question 1

What does LR stand for?

Answer 1

Link Register

Question 2

What does SP stand for?

Answer 2

Stack Pointer

Question 3

What does FP stand for?

Answer 3

Frame pointer

Question 4

In ARM, the r15 is what?

Answer 4

The PC

Question 5

In ARM, the r14 is what?

Answer 5

The Link Register (LR)

Question 6

In ARM, the r13 is what?

Answer 6

The Stack Pointer (SP)

Question 7

In ARM, the r11 is what?

Answer 7

The Frame Pointer (FP)

Question 8

In ARM, the r11 is what?

Answer 8

The Frame Pointer (FP)

Question 9

What is “sign-extension”

Answer 9

Copying the leading bit, or “extending” it to fill the leading spaces when the value is copied, effectively extending the plus or minus sign to an extent

Question 10

What is “sign-extension”

Answer 10

Copying the leading bit, or “extending” it to fill the leading spaces when the value is copied, effectively extending the plus or minus sign to an extent

Question 11

Is LDR r0, = 0x12234 a pseudo instruction?

Answer 11

Yes

Question 12

is ADR r0, label a psuedo instruction?

Answer 12

Yes

Question 13

is NEG a psuedo instruction?

Answer 13

Yes

Question 14

What do TEQ, TST, CMP, and CMN do exactly?

Answer 14

CMP = r0 - r1

CMN = r0 - (-r1)

TST = ANDs the two operands together (usually used for testing individual bits)

TEQ = Performs an EORS on the two operands and discards the results

Question 15

CMP and CMN update which flags?

Answer 15

All flags

Question 16

What do SBC and RSC do?

Answer 16

Subtract with carry and reverse subtract with carry

Question 17

Difference between NEG and MVN?

Answer 17

NEG specifically subtracts the number from 0 and stores it in a register. It is a pseudo instruction.

MVN moves the logical complement (flipping every 1 to 0 and every 0 to 1)

Question 18

LSL is a pseudo instruction. How does ARM implement it?

Answer 18

MOV r3, r3, LSL #

Question 19

LSR is a pseudo instruction. How does ARM implement it?

Answer 19

MOV r3, r3, LSR #

Question 20

ASR is a pseudo instruction. How does ARM implement it?

Answer 20

MOV r3, r3, ASR #

Question 21

ROR is a pseudo instruction. How does ARM implement it?

Answer 21

MOV r3, r3, ROR #

Question 22

RRX is a pseudo instruction. How does ARM implement it?

Answer 22

MOV r3, r3, RRX

Question 23

Logical shifts always occur ____ the operand is use for anything

Answer 23

BEFORE