Chapter 3: Flow Control, Branch/Data Processing Instructions, and Addressing Modes

Question 1

What is unconditional branching?

Answer 1

Branch always, branch without a condition

Question 2

What is conditional branching?

Answer 2

branches depending on the status the CPSR

Question 3

How many bits does ARM dedicate in each instruction to encode conditions?

Answer 3

4 bits

Question 4

How many possible different conditions are there in ARM?

Answer 4

16 difference conditions

Question 5

Of ARM’s ___ different conditions, how many are dedicated to a single bit in the CPSR (N, Z, V, C)?

Answer 5

There are 16 possible conditions

Eight possible conditions:

• Four for true
• Four for false

Question 6

Of ARM’s ___ different conditions, how many are dedicated to compound conditions?

Answer 6

There are 16 possible conditions:

• Six are dedicated to compound conditions

Question 7

Of ARM’s ___ different conditions, what are the conditions dedicated to non-CPSR related conditions?

Answer 7

There are 16 possible conditions:

• One is dedicated to ALWAYS
• One is dedicated to NEVER

Question 8

What does a while loop in ARM look like?

Answer 8

While CMP r0, #0
BNE Exit

        {code...}

        B   While Exit      {Post-loop}

Question 9

What does a Repeat-Until loop in ARM look like?

Answer 9

Repeat {code…}

            CMP r0, #0
            BNE Repeat

           {Post-loop}

Question 10

What does a for loop in ARM look like?

Answer 10

MOV r0, #10

Loop {code}

         SUBS r0, #1
         BNE Loop

         {Post-loop}

Question 11

A repeat-until loop….

Answer 11

Carries out the code while the condition is false

Question 12

ARM branch instructions have to keep in mind what?

Answer 12

The pipelining effect of the PC, which is 2 instructions ahead always

Question 13

The PC is always ____ instructions or ____ bytes ahead of the current instructions

Answer 13

2 instructions ahead

or 8 bytes

Question 14

Rotate Right Through Carry (RRX) is encoded as what?

Answer 14

Rotate right with zero shift

Question 15

When appending an S to conditional code, the S can go where?

Answer 15

Before or after the condition

ADDEQS & ADDSEQ

are both valid

Question 16

When there is no shift at all, what it is encoded as?

Answer 16

Logical left (00) with 0 shift (00000)

Question 17

In all test and compare instructions, the destination register field must be….

List the instructions

Answer 17

Encoded as 0000 and S = 1

TST
CMP
TEQ
CMN

Question 18

In all moving instructions, the register source 1 must be encoded as…

Answer 18

0000

MOV
MVN

Question 19

When encoding literals, rotations are always…

Answer 19

Rotating right

Question 20

When encoding literals, the ENCODED rotation is always…

Answer 20

Doubled before being used

Question 21

When encoding literals, ARM encodes ____ bits as the total, ____ of which are the rotation, and the remaining _____ is the number before rotation…

Answer 21

12 bits total literal,

4 of which are the rotation

8 of which are the number before rotation

Question 22

When encoding literals, the 8 bits must be a value from…

Answer 22

0 to 255

Question 23

The number of rotations must always be

Answer 23

Even, they can never be odd

Question 24

The number of rotations can never be

Answer 24

Odd, must always be even

Question 25

When encoding literals, N rotations right is equal to

Answer 25

32-N rotations left

Question 26

If, after alignment, the number cannot be encoded in _____ bytes….

Answer 26

1 bytes (8 bits), the number cannot be encoded

Question 27

To align the pattern of the literal,

Answer 27

Augment the pattern by zeros to make it 8 bits in total (the 0-to-255 value). Make sure that the number of the other zeros to the left and to the right are even, OR the length of left and right pattern are even

Question 28

What are the three kinds of addressing modes?

Answer 28

Literal, Register Direct, and Register Indirect

Question 29

What addressing modes are supported by ARM?

Answer 29

Literal and Register Indirect

Question 30

What addressing mode is not supported in ARM?

Answer 30

Register Direct?

Question 31

What is literal addressing?

Answer 31

loading a register with a literal amount in the instruction

Question 32

What is Register Direct addressing?

Answer 32

load the contents of a memory location into a register

not supported by ARM

Question 33

What is Register Indirect addressing?

Answer 33

load a register with the contents of a memory location pointed at by a register

Question 34

In register indirect addressing, what is the format?

Answer 34

Indicated by means of square brackets:
LDR r1,[r0]

;[r1] ← [[r0]]

Question 35

What is base plus displacement addressing?

Answer 35

The effective address of an operand is computed by adding the contents of a register to a literal offset encoded into the load/store instruction

Question 36

In ARM indirect addressing, the offset can be…

Answer 36

A second register so that you can use a dynamic offset that can be modified at runtime:

LDR r2,[r0,r1]
;[r2] ← [[r0] + [r1]]

Question 37

In ARM indirect addressing, what can be used to SCALE an offset?

Answer 37

Logical shifts can also be used to scale an offset:

LDR r2,[r0,r1,LSL #2] ;[r2] ← [[r0] + [r1] × 4]

Question 38

What are the two types of auto-indexing modes in ARM?

Answer 38

Auto-indexing pre-indexed

Auto-indexing post-indexed

Question 39

What is pre-indexing in ARM? What is the syntax?

Answer 39

Pre-Index: LDR r0,[r1,#8]!

Load r0 with contents of memory location stored in (r1 + 8) and then increment r1 by 8

The offset can also be an index register, for example, “r2” instead of “#12”, or can be an index register with shift, for example, “r2,LSL#3” instead of “#12”

Question 40

What is post-indexing in ARM? What is the syntax?

Answer 40

Post-Index: LDR r0,[r1],#8

Load r0 with the contents pointed at by r1 and then increment r1 by 8

The offset can also be an index register, for example, “r2” instead of “#12”, or can be an index register with shift, for example, “r2,LSL#3” instead of “#12”