Chapter 3: Flow Control, Branch/Data Processing Instructions, and Addressing Modes Flashcards
What is unconditional branching?
Branch always, branch without a condition
What is conditional branching?
branches depending on the status the CPSR
How many bits does ARM dedicate in each instruction to encode conditions?
4 bits
How many possible different conditions are there in ARM?
16 difference conditions
Of ARM’s ___ different conditions, how many are dedicated to a single bit in the CPSR (N, Z, V, C)?
There are 16 possible conditions
Eight possible conditions:
- Four for true
- Four for false
Of ARM’s ___ different conditions, how many are dedicated to compound conditions?
There are 16 possible conditions:
- Six are dedicated to compound conditions
Of ARM’s ___ different conditions, what are the conditions dedicated to non-CPSR related conditions?
There are 16 possible conditions:
- One is dedicated to ALWAYS
- One is dedicated to NEVER
What does a while loop in ARM look like?
While CMP r0, #0
BNE Exit
{code...}
B While Exit {Post-loop}
What does a Repeat-Until loop in ARM look like?
Repeat {code…}
CMP r0, #0
BNE Repeat
{Post-loop}
What does a for loop in ARM look like?
MOV r0, #10
Loop {code}
SUBS r0, #1
BNE Loop
{Post-loop}
A repeat-until loop….
Carries out the code while the condition is false
ARM branch instructions have to keep in mind what?
The pipelining effect of the PC, which is 2 instructions ahead always
The PC is always ____ instructions or ____ bytes ahead of the current instructions
2 instructions ahead
or 8 bytes
Rotate Right Through Carry (RRX) is encoded as what?
Rotate right with zero shift
When appending an S to conditional code, the S can go where?
Before or after the condition
ADDEQS & ADDSEQ
are both valid
When there is no shift at all, what it is encoded as?
Logical left (00) with 0 shift (00000)
In all test and compare instructions, the destination register field must be….
List the instructions
Encoded as 0000 and S = 1
TST
CMP
TEQ
CMN
In all moving instructions, the register source 1 must be encoded as…
0000
MOV
MVN
When encoding literals, rotations are always…
Rotating right
When encoding literals, the ENCODED rotation is always…
Doubled before being used
When encoding literals, ARM encodes ____ bits as the total, ____ of which are the rotation, and the remaining _____ is the number before rotation…
12 bits total literal,
4 of which are the rotation
8 of which are the number before rotation
When encoding literals, the 8 bits must be a value from…
0 to 255
The number of rotations must always be
Even, they can never be odd
The number of rotations can never be
Odd, must always be even
When encoding literals, N rotations right is equal to
32-N rotations left
If, after alignment, the number cannot be encoded in _____ bytes….
1 bytes (8 bits), the number cannot be encoded
To align the pattern of the literal,
Augment the pattern by zeros to make it 8 bits in total (the 0-to-255 value). Make sure that the number of the other zeros to the left and to the right are even, OR the length of left and right pattern are even
What are the three kinds of addressing modes?
Literal, Register Direct, and Register Indirect
What addressing modes are supported by ARM?
Literal and Register Indirect
What addressing mode is not supported in ARM?
Register Direct?
What is literal addressing?
loading a register with a literal amount in the instruction
What is Register Direct addressing?
load the contents of a memory location into a register
not supported by ARM
What is Register Indirect addressing?
load a register with the contents of a memory location pointed at by a register
In register indirect addressing, what is the format?
Indicated by means of square brackets:
LDR r1,[r0]
;[r1] ← [[r0]]
What is base plus displacement addressing?
The effective address of an operand is computed by adding the contents of a register to a literal offset encoded into the load/store instruction
In ARM indirect addressing, the offset can be…
A second register so that you can use a dynamic offset that can be modified at runtime:
LDR r2,[r0,r1]
;[r2] ← [[r0] + [r1]]
In ARM indirect addressing, what can be used to SCALE an offset?
Logical shifts can also be used to scale an offset:
LDR r2,[r0,r1,LSL #2] ;[r2] ← [[r0] + [r1] × 4]
What are the two types of auto-indexing modes in ARM?
Auto-indexing pre-indexed
Auto-indexing post-indexed
What is pre-indexing in ARM? What is the syntax?
Pre-Index: LDR r0,[r1,#8]!
Load r0 with contents of memory location stored in (r1 + 8) and then increment r1 by 8
The offset can also be an index register, for example, “r2” instead of “#12”, or can be an index register with shift, for example, “r2,LSL#3” instead of “#12”
What is post-indexing in ARM? What is the syntax?
Post-Index: LDR r0,[r1],#8
Load r0 with the contents pointed at by r1 and then increment r1 by 8
The offset can also be an index register, for example, “r2” instead of “#12”, or can be an index register with shift, for example, “r2,LSL#3” instead of “#12”
