Chapter 3: Assembler Info Flashcards
The code to set up an area is:
AREA nameOfCode, CODE, READONLY
ENTRY
{code}
END
{label} DCD v. expr {, v. expr}
Does what?
set up one or more 32-bit (4 byte) constant in memory. MUST START AT A MULTIPLE OF 4 ADDRESS
{label} DCW v. expr {, v. expr}
Does what?
set up one or more 16-bit (2 byte) constant in memory. MUST START AT A MULTIPLE OF 2 (EVEN) ADDRESS
{label} DCB v. expr {, v. expr}
Does what?
set up one or more 8-bit (1 byte) constant in memory. CAN START ANYWHERE
{label} SPACE size (in bytes) expr
Does what?
reserve a zeroed block of memory
ALIGN
Does what?
ensures that the next data item is correctly aligned on a 32-bit boundary (start at a multiple of 4)
If no align is included…
the assembler will automatically insert bytes with zeros to ensure appropriate boundary alignment
DCD, DCW, and DCB tell the assembler to:
- Reserve one or more 32-bit, 16-bit, or 8-bit blocks of storage in memory
- Load whatever values to the right of DCD, DCW, or DCB into the locations
- Advance the location-counter by one or more four, two, or one bytes so that the next instruction will be put in the next place in memory
What is the location-counter?
a variable inside the assembler to keep track of memory locations during assembling a program, whereas the PC is a register to keep track of the next instruction to be executed
What is the difference between the PC and the location-counter?
Location-Counter is a variable inside the assembler to keep track of memory locations during assembling a program, whereas the PC is a register to keep track of the next instruction to be executed
ALIGN is an example of
explicit alignment
Strings must
BE ALLOCATED WITH DCB AND DOUBLE QUOTES “ ”
Single characters must
ALSO ALLOCATED WITH DCB BUT WITH SINGLE QUOTES INSTEAD ‘ ‘
& can represent
DCD if used in place of DCD (P1 & 0x12345678)
0x if used after a DCD, DCW, or DCB (Strg2 = “X2”, &0C, &0A )
= can represent
DCB if used in place of DCB (Strg2 = “X2”, &0C, &0A )
% represents
SPACE
A pseudo instruction is
an operation the programmer can use when writing code
Pseudo instructions do not
Have machine language equivalents
MOV cannot
move anything longer than 16-bits long (FFFF) is maximum
Instead of using MOV for a 17+ bit literal, use
LDR r0, = 0xFFFFFF pseudo instruction
LDR r0, = 0xFFFFFF pseudo instruction
Does what?
Loads FFFFFF into r0
ADR r0, label
Does what?
loads a 32-bit address into a register
What is the difference between ADD and ADC?
ADD and ADDS: adds two 32-bit values
ADC and ADCS: adds two 32-bit values together with carry
ADDS and ADCS update which flags?
ADDS and ADCS update ALL FLAGS
What is the difference between SUB and RSB?
SUB: SUB r1,r2,r3 means subtract r3 from r2 and store in r1
RSB: RSB r1,r2,r3 means subtract r2 from r3 and store in r1
RSB can be used to subtract from a constant:
RSB r1, r2, #10
RSB can be shortened: RSB r1, #5 means RSB r1, r1, #5
SUBS and RSBS update which flags?
SUBS and RSBS update ALL FLAGS
NEG does what?
NEG (Negation): is a pseudo instruction to subtract a number from zero
NEG only has two operands and CANNOT be shortened
NEG r1, r2 is equal to RSB r1, r2, #0
NEG r1, r2 is equal to…
RSB r1, r2, #0
What is the difference between MOV and MVN?
MOV: MOV r0, r1 moves contents of r0 into r1
MVN: MOV r0, r1 moves the logical complement of r1 (every 1 to 0 and every 0 to 1) into r0
MOVS and MVNS update which flags?
MOVS and MVNS update the N, Z, and C flags, NOT the V flag
What does MUL do exactly?
MUL rd, rm, rs multiplies rm by rs and stores the lower-order 32-bits of the 64-bit operation (cannot be shortened to 2 operands)
CANNOT use the same register for rd and rm
ARM does not allow multiplying by a constant
Does arm support multiplying by a constant?
No
For multiplying, can you use the same register for destination and register source 1?
No
For multiplying, can you use the same register for destination and register source 2?
Yes
MLA does what?
MLA: MLA rd, rm, rs, rn = (rm x rs) + rn. Cannot be shortened to three operands
MULS and MLAS update which flags?
MULS and MLAS update the N and Z flags, but CORRUPT the C and V flags
MVN does what to 11001010?
will not EVERY bit, INCLUDING the leading zeros:
11111111111111111111111100110101
ANDS, ORRS, EORS, and MVNS update which flags?
ANDS, ORRS, EORS, and MVNS update the N, Z, and C flags, NOT the V flag
What does the 2_ sign prefix indicate?
Binary
What does the 8_ sign prefix indicate?
Octal
What does the 0x sign prefix indicate?
Hexadecimal
What does the & sign prefix indicate?
Hexadecimal
BIC does what?
BIC (bit clear) ANDs its first operand with the complement of the second
Example: suppose we have r1 = 10101010 and r2 = 00001111.
The instruction BIC r0, r1, r2 yield 10100000
BICS updates which flags?
BICS updates the N, Z, and C flags, NOT the V flag
What is the difference between implicit and explicit updating of flags?
Example of implicit updates for the condition flags: SUBS r1,r1,r2
Example of explicit updates for the condition flags CMP r1,r2
What does CMP r1, r2 do?
evaluates r1 - r2 and sets the flags without storing the result
What does TEQ r1, r2 do?
Tests whether r1 is equal to r2
similar to EORS, except that the result is discarded
What does TST r1, r2 do?
TST (test instruction) Compares two operands by ANDing them together and update flags. Usually used to test individual bits; TST r0, #2_00100000 ;AND r0 with 00100000 to test bit 5
What does CMN r1, r2 do?
CMN (compare negative instruction). 2’s complements the second operand before performing the comparison: CMN r1, r2 ; evaluates [r1] – (-[r2])
What is a logical shift?
Insert a 0 in the vacated positions
What is an arithmetic shift?
replace the sign bit during a right shift
What is a circular shift?
the bit shifted out of one end is places into the other
What is a Circular shifts through carry?
Include the carry bit in the shift path
Does arm have any explicit shift operation?
No
What can ARM do with shift operations?
ARM can combine shifting operations with other data processing operations where the second operand is allowed to be shifted BEFORE it is used
ADD r0,r1,r2,LSL #1 ;
[r0] < [r1] + [r2] × 2
LSL r3, r3, #1 is equal to
MOV r3, r3, LSL #1 which is equal to LSL r3, #1
MOV r3, r3, LSL #1 is equal to
LSL r3, r3, #1 which is equal to LSL r3, #1
LSL is a
pseudo instruction
ARM supports both ____ and ____ shifts
Static and dynamic
For LSL, allowable values are from
0 to #31 (32 different values)
For LSR, allowable values are from
1 to #32 (32 different values)
For ASR, allowable values are from
1 to #32 (32 different values)
For ROR, allowable values are from
1 to #31 (31 different values)
For dynamic shifts, the following mean what?
MOV r4,r3,LSL r2
LSL r4,r3,r2
MOV r4,r3,LSL r2 ;
[r4] [r3] × 2^r2
LSL r4,r3,r2
;[r4] [r3] × 2^r2
If, for a shift operation, the value of the register storing the dynamic amount is greater than 32, what will be stored in the destination?
Zeros
What are the five shift types supported by ARM?
LSL logical shift left
LSR logical shift right
ASR arithmetic shift right
ROR rotate right
RRX rotate right through carry (one shift)
Arithmetic shift left is the same as
a logical shift left
Rotate left through carry can be implement by
ADCS r0,r0,r0 ; add r0 to r0 with carry and set the flags
The instruction means r0 + r0 + C, i.e., 2 × r0 + C
What are the two ways of loading addresses into a register?
LDR r0, =PPP
ADR r0, PPP
What is the order of the data definition if it were to be negative, and hex? Octal?
-8_15 = octal
#-0xFC = hex Starts with the # sign Followed by the optional positive or negative sign Followed by an optional base sign Followed by the number
