Week 7 Flashcards
today’s technology uses _____ distinct voltages to represent all info
2
_____ circuit: have reference voltages, respond to input near reference voltage as if the input were that reference voltage, change circuit output fast
digital
same everyone on given wire, proportional to energy, each end is a terminal
voltage
CMOS Logic circuit:
fast, small, low power, cheap
NAND Truth table
A B (A&B)’
0 0 1
0 1 1
1 0 1
1 1 0
half-adder
AND and XOR gate,
circuit to perform addition,
two input bits -> sum and carry out bit
full adder
2 half-adders and carry output, OR gate provides a carry output if either of the half adders report a carry
How many inputs are needed for a full adder?
6: Logically, 2^3 = 8, (1 carry in, bit 1, bit 2) but bit 1 and 2 are treated symmetrically, so only 6 are needed.
what’s the point of mini-truth tables in larger truth tables?
It means circuits can be removed / you can save on space
diagram grammar:
input->logic->output
sum of products:
OR the ANDs: xy+x’y’
minterms
find the 1 outputs
ORing the minterms gives 1 as expression
product of sums:
AND the ORs: (x’ + y) * (x + y’)
maxterms
find the 0s then AND them together
useful tip: think it through and set the terms equal to eachother and think of outputs you want to get.
what to do with extra inputs?
make them cheap
propogation delay:
elapsed time from gate input change to corresponding gate output change
Switch
Joins two wires to make one wire when in the on position
De Morgan’s Laws and Gate equivalences
(AB)’ = A’ + B’ ( NAND = NOT A or NOT B)
(A+B) = A’B’ (NOR = NOT A and NOT B)
Outputs are a function of the sequence of previous inputs as well as the current input
Sequential circuit
Remembers the value the input had while the enable line(extra input) was set
Latch
A register uses a set of _____ to store a digital value
Latches
Active High Logic
Truth table logic 1 values with the higher voltage level of the two
Active Low Logic
Logic 1 value with the lower voltage level of the two
Time for a logic circuit to compute a result
Gate Delay
