Week 6 Flashcards
4 Mneumonics (Instruction Operators)
ADD, LOAD, STORE, JUMP
In most assembly languages, the target register goes _____ the source register
before
two parts of memory operands:
register and a constant (OFFSET)
general process when instruction is executed
processor reads the current value from register, adds offset, uses result as memory address
ex: LOAD r1, 20(r3)
r1 is what data will be loaded into, add 20 (offset) to r3 to get desired memory address
ex: JUMP 60(r11)
add 60 (offset) to r11, treat result as address in instruction memory
_____ contains value that specifies operation
opcode field
5 bit opcode implies ___ instructions
<=32 (2^5)
a register is a _____ value
pointer
offset is a _____ integer
2’s complement
3 steps hardware repeats:
use instr ptr to fetch instruction, use bits in instr to control hardware that performs operation, move instr ptr to next instr
choice of what statement to execute next
control flow
3 control flow paradigms:
sequential, skip ahead, step back
instr_bus <- Instr. memory[Current_Instr_Adder]
sequential
2 ways actual_next_instruction can be known:
statically (ahead of time; at compile time; Ex: Ordinary Statement) or dynamically (only known through executing program; Ex: while loop)
hardware separates fields of instruction such as ___
operations, registers, and offset
computers have ___ that coordinate data movement
controllers
1 output for K inputs
multiplexer
operation fields are passed to the _____
ALU
fastest to slowest operand types:
immediate operands, register operands, main memory
CMOS favors ISAs with:
fixed-length instructions, simple field structure within representation, small ISA compiler can fully use
Add
Add the integers in two registers and place the result in a third register
Load
Load an integer from the data memory into a register
Store
Store the integer in a register into the data memory
Jump
Jump to a new location in the instruction memory
Instruction pointer
Consists of a register(set of latches) in the processor that holds the memory address of the next instruction to execute
Absolute Branch
Computes a memory address that specifies the location of the next instruction to execute
Relative Branch
positive or negative increment for the program counter
Current Instruction
Instruction of the current fetch execute cycle
Program counter(PC)
Register that contains the pointer to the Current instruction
Instruction Decoding
Hardware separates fields of the instruction
Locality of Reference
Programs with large numbers of memory operands use them in small batches at a time
