Verilog Tutorials Flashcards
HDL
hardware description language - used to describe the structure and operation of digital systems
where are semicolons needed
end of module initiation and after code statements
not needed after endmodule or after if / begin / end
how to declare input variables
input variable;
how to declare output variables
output variable;
data types
wire:
wire wire1, wire2;
registers:
reg [3:0] clk;
how do verilog constants work?
<# of bits> ‘ <base></base> <number></number>
structural verilog coding
describe logic using built-in primitives
- interconnection of simple components
- purely structural
- executed concurrently
- one output
- uses words for logic operators
Dataflow verilog coding
- specify output signals in terms of input signals
- specifies transfer of data between registers
- some structural info available
behavioral verilog coding
- algorithmically specify design behavior
- procedural code similar to C
- little structural detail
structural verilog coding example
module AND(out, i0, i1)
input io, i1;
output out;
and (out, io, i1)
endmodule
true or false: wires must be initialized in first line of module
false
data flow description eg
uses assign statements
does data flow description use continuous assignment?
yes
logical operators description
always returns 1-bit result, interpreted as false when all bits are zero, true when atleast one bit is one
Use ______ operators for boolean expressions and use ______ operators for signal manipulation
logical, bitwise
