Chapter 4 Flashcards

1
Q

combinational circuit

A

consists of logic gates whose outputs are determined from only the present combination of inputs

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2
Q

a combinational circuit performs an operation that can be specified logically either by ___________ or ___________

A

a set of boolean functions
truth table

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3
Q

design procedure for combinational circuit

A
  1. specification
  2. formulation
  3. optimization
  4. verification
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4
Q

specification

A

label input and output

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5
Q

formulation

A

derive a truth table or boolean equations that define the relationship between the inputs and outputs

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6
Q

optimization

A

use k map and draw a logic diagram

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7
Q

verification

A

use CAD tools to verify the final design with simulation

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8
Q

practical considerations of a combinational circuit

A
  • number of gates
  • max allowed delay
  • max consumed power
  • working conditions
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9
Q

excess-3 code converter

A

add three to the number

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10
Q

Half adder

A

addition of two bits, results in two outputs: sum and carry

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11
Q

full adder

A

addition of three bits to account for carry bit from previous digit, results in two outputs: sum and carry

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12
Q

ripple carry adder

A

aka binary adder - created by connecting cascading full adders
addition of n-bit numbers needs n full adders

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13
Q

input carry of binary adder ________

A

is fixed at 0

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14
Q

four-bit adder is an example of a _____________

A

standard component or modular design

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15
Q

for an n-bit adder, there are ____ gate levels for the carry to get from input to output

A

2n

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16
Q

binary subtractor basic principal

A

for unsigned binary numbers, take the 2’s complement of subtrahend and add them together

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17
Q

binary subtractor gate explanation

A

for A-B:
- each digit of B is xored with an extra input (M) to take 2’s complement before entering the FA
- M is 1 for subtraction, 0 for addition
- M is also the carry input for the first digit

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18
Q

Decoder

A
  • converts binary information from n input lines to a max of 2^n unique output lines
  • at any time there will be exactly one output set to 1, the rest are 0
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19
Q

enable input of decoder

A
  • En
  • controls encoder operation so that when En=0, there is no output and when its 1 the decoder functions as normal
20
Q

DECODER: if you have 3 inputs (x0,x1,x2) and 8 outputs (y0…y7) what would first line of truth table look like

A

x2 x1 x0 y0 y1 y2 y3 y4 y5 y6 y7
0 0 0 1 0 0 0 0 0 0 0

21
Q

how do you create a full adder from a half adder

A

input x and y go to first HA, then sum1 and z go into second half adder, sum2 = final sum and carry1 is ored with carry2 to get final carry

22
Q

applications of decoders

A
  1. selection of peripheral devices - select/deselect things like hard disk, cd drive etc
  2. instruction decoder - computer programs based on instructions that are decoded by the computer hardware and implemented
23
Q

how can any combinational circuit be implemented with a decoder

A

for n inputs and m outputs, use n to 2^n decoder and m OR gates
- can be used since boolean function can be expressed in standard sop form
- all minterms that satisfy one output variable are ored

24
Q

encoder description

A
  • performs inverse operation of a decoder
  • 2^n inputs and n outputs
  • assumed only one input has a value of 1 at a time
25
encoder gate description
- find truth table for outputs - each output is gotten by oring all inputs that result in that output being 1
26
priority encoder
- has priority for if more than 1 input is 1 at a time
27
would y3 or y0 have higher priority in an encoder
y3
28
what is the third output of a priority encoder
V - valid bit indicator set to 1 when one or more inputs are equal to 1, if all inputs are 0, V is 0
29
when are the outputs of a priority encoder dont cares
when V=0 the other outputs are not inspected
30
multiplexer description
- 2^m to 1 multiplexer has 2^m inputs and m select inputs
31
select inputs
used in multiplexer to route data from 2^m inputs to the single output
32
multiplexer reminder 2 to 1
f = s'w0 + sw1 so when s is 0, w0 occurs when s is 1, w1 occurs
33
4 to 1 MUX truth table
s0 s1 f 0 0 w0 0 1 w1 1 0 w2 1 1 w3
34
draw a 2 to 1 multiplexer
just do it - its lecture 19 slide 23
35
a multiplexer is essentially __________
a decoder that includes the OR gate within the unit
36
demultiplexer
- can deliver multiple outputs from a single inputs
37
the data/ input to a demux ______
must be 1 to create any outputs
38
the outputs of a demux are controlled by ________
1st - data must be 1 2nd - uses n control inputs to decide which of 2^n outputs occurs
39
digital comparator
- compares the values of two inputs (greater than, less than, or equal)
40
2 types of digital comparators
identity comparator magnitude comparator
41
identity comparator
only one output, if A=B, then output is one, otherwise its zero
42
magnitude comparator
three output terminals, one for each type of equality
43
boolean expression for A
A'B
44
boolean expression for A>B
A'B
45
boolean expression for A=B
(A'B+B'A)'
46
multi bit comparators
use n cascading comparators to compare n-bit values