Chapter 4 Flashcards
combinational circuit
consists of logic gates whose outputs are determined from only the present combination of inputs
a combinational circuit performs an operation that can be specified logically either by ___________ or ___________
a set of boolean functions
truth table
design procedure for combinational circuit
- specification
- formulation
- optimization
- verification
specification
label input and output
formulation
derive a truth table or boolean equations that define the relationship between the inputs and outputs
optimization
use k map and draw a logic diagram
verification
use CAD tools to verify the final design with simulation
practical considerations of a combinational circuit
- number of gates
- max allowed delay
- max consumed power
- working conditions
excess-3 code converter
add three to the number
Half adder
addition of two bits, results in two outputs: sum and carry
full adder
addition of three bits to account for carry bit from previous digit, results in two outputs: sum and carry
ripple carry adder
aka binary adder - created by connecting cascading full adders
addition of n-bit numbers needs n full adders
input carry of binary adder ________
is fixed at 0
four-bit adder is an example of a _____________
standard component or modular design
for an n-bit adder, there are ____ gate levels for the carry to get from input to output
2n
binary subtractor basic principal
for unsigned binary numbers, take the 2’s complement of subtrahend and add them together
binary subtractor gate explanation
for A-B:
- each digit of B is xored with an extra input (M) to take 2’s complement before entering the FA
- M is 1 for subtraction, 0 for addition
- M is also the carry input for the first digit
Decoder
- converts binary information from n input lines to a max of 2^n unique output lines
- at any time there will be exactly one output set to 1, the rest are 0
enable input of decoder
- En
- controls encoder operation so that when En=0, there is no output and when its 1 the decoder functions as normal
DECODER: if you have 3 inputs (x0,x1,x2) and 8 outputs (y0…y7) what would first line of truth table look like
x2 x1 x0 y0 y1 y2 y3 y4 y5 y6 y7
0 0 0 1 0 0 0 0 0 0 0
how do you create a full adder from a half adder
input x and y go to first HA, then sum1 and z go into second half adder, sum2 = final sum and carry1 is ored with carry2 to get final carry
applications of decoders
- selection of peripheral devices - select/deselect things like hard disk, cd drive etc
- instruction decoder - computer programs based on instructions that are decoded by the computer hardware and implemented
how can any combinational circuit be implemented with a decoder
for n inputs and m outputs, use n to 2^n decoder and m OR gates
- can be used since boolean function can be expressed in standard sop form
- all minterms that satisfy one output variable are ored
encoder description
- performs inverse operation of a decoder
- 2^n inputs and n outputs
- assumed only one input has a value of 1 at a time
encoder gate description
- find truth table for outputs
- each output is gotten by oring all inputs that result in that output being 1
priority encoder
- has priority for if more than 1 input is 1 at a time
would y3 or y0 have higher priority in an encoder
y3
what is the third output of a priority encoder
V - valid bit indicator
set to 1 when one or more inputs are equal to 1, if all inputs are 0, V is 0
when are the outputs of a priority encoder dont cares
when V=0 the other outputs are not inspected
multiplexer description
- 2^m to 1 multiplexer has 2^m inputs and m select inputs
select inputs
used in multiplexer to route data from 2^m inputs to the single output
multiplexer reminder 2 to 1
f = s’w0 + sw1
so when s is 0, w0 occurs
when s is 1, w1 occurs
4 to 1 MUX truth table
s0 s1 f
0 0 w0
0 1 w1
1 0 w2
1 1 w3
draw a 2 to 1 multiplexer
just do it - its lecture 19 slide 23
a multiplexer is essentially __________
a decoder that includes the OR gate within the unit
demultiplexer
- can deliver multiple outputs from a single inputs
the data/ input to a demux ______
must be 1 to create any outputs
the outputs of a demux are controlled by ________
1st - data must be 1
2nd - uses n control inputs to decide which of 2^n outputs occurs
digital comparator
- compares the values of two inputs (greater than, less than, or equal)
2 types of digital comparators
identity comparator
magnitude comparator
identity comparator
only one output, if A=B, then output is one, otherwise its zero
magnitude comparator
three output terminals, one for each type of equality
boolean expression for A<B
A’B
boolean expression for A>B
A’B
boolean expression for A=B
(A’B+B’A)’
multi bit comparators
use n cascading comparators to compare n-bit values
