Chapter 5 Flashcards

1
Q

sequential circuit

A

outputs are a function of the inputs and the state of the storage elements (aka past inputs)

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2
Q

synchronous sequential circuits

A

behavior can be defined from the signals at discrete instants of time, uses a clock signal

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3
Q

asynchronous sequential circuit

A

behavior depends on input signals at any instant of time and the order in which the inputs change
- use time delay storage elements

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4
Q

latches

A
  • storage elements that work with signal levels
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5
Q

level sensitive devices

A

operate with signal levels (0 or 1)

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6
Q

edge sensitive devices

A

operate with signal transitions (high to low or low to high)

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7
Q

flip flops are ______ sensitive devices

A

edge

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8
Q

S-R Latch

A

-2 cross coupled NOR or AND gates
- has 2 inputs: S and R

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9
Q

S-R latch truth table

A

S R Q Q’
1 0 1 0 (set)
0 1 0 1 (reset)
0 0 x x (Q doesnt change)
1 1 0 0 (forbidden)

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10
Q

S-R latch with control input

A

third input, En, is NANDed with both inputs before going into S-R latch
if En is 0, there is no change

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11
Q

D-Latch

A

gets rid of forbidden state of S-R latch, has only 2 inputs (D and En), D fulfills role of S and R by going through a not gate to become R

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12
Q

D-Latch truth table

A

D Next
0 Reset
1 Setq

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13
Q

flip flop

A
  • 1 bit memory element
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14
Q

the output-input relationship of a FF is defined by a _______ or _______

A

characteristic table or characteristic equation

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15
Q

direct inputs

A
  • inputs that set or reset their states independent of the clock, so come in through bottom of diagram
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16
Q

D flip flop construction

A
  • master-slave flip flop
  • uses two D latches and an inverter
  • Output of flip flop 1 fed to FF2
  • regular clock enters FF1(master) and then is inverted before entering FF2 (slave)
17
Q

D FF

A
  • input enters master latch when clock goes up, then when clock goes down that information transfers to the slave latch/final output
18
Q

draw a JK flipflop

A
  • J, Q’ and Clk enter a NAND gate (output w1)
  • K, Q, and clk enter a NAND gate (output w2)
  • w1 and Q’ enter a NAND gate (output Q)
  • w2 and Q enter a NAND gate (output Q’)
19
Q

T Flip Flop from JK

A

a j-k flip flop when J and K are tied together

20
Q

basic principle of T FF

A

complementing or not complementing last state

21
Q

Latches are faster or slower than FF

A

faster

22
Q

form of state equations

A

A(t+1) = Ax+B’x

23
Q

is the output of a sequential circuit in the form y(t+1) or y(t)

A

y(t)

24
Q

parts of a state table

A

present state, input, next state, output

25
Q

state diagrams have a form x/x on the arrow, which is each?

A

input/output

26
Q

what is in the circles on state diagrams

A

state of flip flops

27
Q

steps of analysis of clocked sequential circuit

A

circuit diagram
state equations
state table
state diagram

28
Q

Moore machine

A

output only depends on current states

29
Q

Mealy machine

A

output depends on current states and inputs

30
Q

what does a characteristic table describe

A

flip flop operations

31
Q

excitation table def

A

values of FF inputs for a given state transition

32
Q

sequential circuit design procedure

A
  1. derive state diagram
  2. assign binary values to the states
  3. obtain binary coded state table
  4. choose the type of FF
  5. derive input equations using next state values and excitation tables
  6. simplify using Kmap
  7. draw logic diagram