Unit 7

Question 1

A computer system with at least two processors. This computer is in contrast to a uniprocessor, which has one, and is increasingly hard to find today.

Answer 1

Multiprocessor

Question 2

Utilizing multiple processors by running independent programs simultaneously.

Answer 2

Task-level parallelism or process-level parallelism

Question 3

A single program that runs on multiple processors simultaneously.

Answer 3

Parallel processing program

Question 4

A set of computers connected over a local area network that function as a single large multiprocessor.

Answer 4

Cluster

Question 5

A microprocessor containing multiple processors (“cores”) in a single integrated circuit. Virtually all microprocessors today in desktops and servers are multicore.

Answer 5

Multicore microprocessor

Question 6

A parallel processor with a single physical address space.

Answer 6

Shared memory multiprocessor (SMP)

Question 7

Speed-up achieved on a multiprocessor without increasing the size of the problem.

Answer 7

Strong scaling

Question 8

Speed-up achieved on a multiprocessor while increasing the size of the problem proportionally to the increase in the number of processors.

Answer 8

Weak scaling

Question 9

A uniprocessor.

Answer 9

SISD or single instruction stream, single data stream

Question 10

A multiprocessor.

Answer 10

MIMD or multiple instruction streams, multiple data streams

Question 11

The conventional MIMD programming model, where a single program runs across all processors.

Answer 11

SPMD or single program, multiple data streams

Question 12

The same instruction is applied to many data streams, as in a vector processor.

Answer 12

SIMD or single instruction stream, multiple data streams

Question 13

Parallelism achieved by performing the same operation on independent data.

Answer 13

Data-level parallelism

Question 14

The basic philosophy of blank is to collect data elements from memory, put them in order into a large set of registers, operate on them sequentially in registers using pipelined execution units, and then write the results back to memory.

Answer 14

vector architecture

Question 15

One or more vector functional units and a portion of the vector register file. Inspired by lanes on highways that increase traffic speed, multiple lanes execute vector operations simultaneously.

Answer 15

Vector lane

Question 16

Increasing utilization of a processor by switching to another thread when one thread is stalled.

Answer 16

Hardware multithreading

Question 17

A thread includes the program counter, the register state, and the stack. It is a lightweight process; whereas threads commonly share a single address space, processes don’t.

Answer 17

Thread

Question 18

A process includes one or more threads, the address space, and the operating system state. Hence, a process switch usually invokes the operating system, but not a thread switch.

Answer 18

Process

Question 19

A version of hardware multithreading that implies switching between threads after every instruction.

Answer 19

Fine-grained multithreading

Question 20

A version of hardware multithreading that implies switching between threads only after significant events, such as a last-level cache miss.

Answer 20

Coarse-grained multithreading

Question 21

A version of multithreading that lowers the cost of multithreading by utilizing the resources needed for multiple issue, dynamically scheduled microarchitecture.

Answer 21

Simultaneous multithreading (SMT)

Question 22

A multiprocessor in which latency to any word in main memory is about the same no matter which processor requests the access.

Answer 22

Uniform memory access (UMA)

Question 23

A type of single address space multiprocessor in which some memory accesses are much faster than others depending on which processor asks for which word.

Answer 23

Nonuniform memory access (NUMA)

Question 24

The process of coordinating the behavior of two or more processes, which may be running on different processors.

Answer 24

Synchronization

Question 25

A synchronization device that allows access to data to only one processor at a time.

Answer 25

Lock

Question 26

A function that processes a data structure and returns a single value.

Answer 26

Reduction

Question 27

An API for shared memory multiprocessing in C, C++, or Fortran that runs on UNIX and Microsoft platforms. It includes compiler directives, a library, and runtime directives.

Answer 27

OpenMP

Question 28

Communicating between multiple processors by explicitly sending and receiving information.

Answer 28

Message passing

Question 29

A routine used by a processor in machines with private memories to pass a message to another processor.

Answer 29

Send message routine

Question 30

A routine used by a processor in machines with private memories to accept a message from another processor.

Answer 30

Receive message routine

Question 31

Collections of computers connected via I/O over standard network switches to form a message-passing multiprocessor.

Answer 31

Clusters

Question 32

Rather than selling software that is installed and run on customers’ own computers, software is run at a remote site and made available over the Internet typically via a Web interface to customers. SaaS customers are charged based on use versus on ownership.

Answer 32

Software as a service (SaaS)

Question 33

Informally, the peak transfer rate of a network; can refer to the speed of a single link or the collective transfer rate of all links in the network.

Answer 33

Network bandwidth

Question 34

The bandwidth between two equal parts of a multiprocessor. This measure is for a worst case split of the multiprocessor.

Answer 34

Bisection bandwidth

Question 35

A network that connects processor-memory nodes by supplying a dedicated communication link between every node.

Answer 35

Fully connected network

Question 36

A network that supplies a small switch at each node.

Answer 36

Multistage network

Question 37

A network that allows any node to communicate with any other node in one pass through the network.

Answer 37

Crossbar network

Question 38

A popular high-speed link today is which stands for Peripheral Component Interconnect Express. It is called a link in that the basic building block, called a serial lane, consists of only four wires: two for receiving data and two for transmitting data. T

Answer 38

PCIe,

Question 39

An I/O scheme in which portions of the address space are assigned to I/O devices, and reads and writes to those addresses are interpreted as commands to the I/O device.

Answer 39

Memory-mapped I/O

Question 40

A mechanism that provides a device controller with the ability to transfer data directly to or from the memory without involving the processor.

Answer 40

Direct memory access (DMA)

Question 41

An I/O scheme that employs interrupts to indicate to the processor that an I/O device needs attention.

Answer 41

Interrupt-driven I/O

Question 42

A program that controls an I/O device that is attached to the computer.

Answer 42

Device driver

Question 43

The process of periodically checking the status of an I/O device to determine the need to service the device.

Answer 43

Polling

Question 44

A UNIX API for creating and manipulating threads. It is structured as a library.

Answer 44

Pthreads

Question 45

The ratio of floating-point operations in a program to the number of data bytes accessed by a program from main memory.

Answer 45

Arithmetic intensity

Question 46

It was perhaps the most infamous of supercomputers. The project started in 1965 and ran its first real application in 1976. The 64 processors used a 13-MHz clock, and their combined main memory size was 1 MB: 64 × 16 KB. The blank was the first machine to teach us that software for parallel machines dominates hardware issues.

Answer 46

Illiac IV