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Computer Architecture > Unit 4 > Flashcards

Unit 4 Flashcards

1
Q

When adding operands with blank, overflow cannot occur.

A

different signs

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2
Q

There are similar restrictions to the occurrence of overflow during subtract, but it’s just the opposite principle: when the signs of the operands are the blank, overflow cannot occur.

A

same

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3
Q

Blank occurs in subtraction when we subtract a negative number from a positive number and get a negative result, or when we subtract a positive number from a negative number and get a positive result.

A

Overflow

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4
Q

Hardware that performs addition, subtraction, and usually logical operations such as AND and OR

A

Arithmetic Logic Unit (ALU)

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5
Q

Which LEGv8 load instructions should be generated for byte and halfword arithmetic operations?

A

LDURB, LDURH

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6
Q

Which LEGv8 arithmetic instructions should be generated for byte and halfword arithmetic operations?

A

ADD, SUB, MUL, DIV

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7
Q

Which LEGv8 store instructions should be generated for byte and halfword arithmetic operations?

A

STURB, STURH

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8
Q

In multiplication, the first operand is called the blank and the second the blank. The final result is called the blank.

A

multiplicand
multiplier
product

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9
Q

In fact, if we ignore the sign bits, the length of the multiplication of an n-bit multiplicand and an m-bit multiplier is a product that is blank long. That is, blank are required to represent all possible products.

A

n + m bits

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10
Q

To produce a properly signed or unsigned 128-bit product, LEGv8 has three instructions: blank, blank and blank

A

multiply (MUL)
signed multiply high (SMULH)
unsigned multiply high (UMULH)

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11
Q

Divide’s two operands, called the blank and blank, and the result, called the blank, are accompanied by a second result, called the blank.

A

dividend and divisor
quotient
remainder

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12
Q

A number being divided.

A

Dividend

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13
Q

A number that the dividend is divided by.

A

Divisor

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14
Q

The primary result of a division; a number that when multiplied by the divisor and added to the remainder produces the dividend.

A

Quotient

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15
Q

The secondary result of a division; a number that when added to the product of the quotient and the divisor produces the dividend.

A

Remainder

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16
Q

A notation that renders numbers with a single digit to the left of the decimal point.

A

Scientific notation

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17
Q

A number in floating-point notation that has no leading 0s.

A

Normalized

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18
Q

Computer arithmetic that represents numbers in which the binary point is not fixed.

A

Floating point

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19
Q

The value, generally between 0 and 1, placed in the fraction field. The fraction is also called the mantissa.

A

Fraction

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20
Q

In the numerical representation system of floating-point arithmetic, the value that is placed in the exponent field

A

Exponent

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21
Q

A situation in which a positive exponent becomes too large to fit in the exponent field.

A

Overflow (floating-point)

22
Q

A situation in which a negative exponent becomes too large to fit in the exponent field.

A

Underflow (floating-point)

23
Q

A floating-point value represented in a 64-bit doubleword.

A

Double precision

24
Q

A floating-point value represented in a 32-bit word.

A

Single precision

25
Q

Also called interrupt. An unscheduled event that disrupts program execution; used to detect overflow.

A

Exception

26
Q

An exception that comes from outside of the processer. (Some architectures use the term interrupt for all exceptions.

A

Interrupt

27
Q

This symbol is NaN, for blank. The purpose of NaNs is to allow programmers to postpone some tests and decisions to a later time in the program when they are convenient.

A

Not a Number

28
Q

LEGv8 supports the IEEE 754 single-precision and double-precision formats with these instructions

A

Floating-point addition, single (FADDS) and addition, double (FADDD)
Floating-point subtraction, single (FSUBS) and subtraction, double (FSUBD)
Floating-point multiplication, single (FMULS) and multiplication, double (FMULD)
Floating-point division, single (FDIVS) and division, double (FDIVD)
Floating-point comparison, single (FCMPS) and comparison, double (FCMPD), with the condition codes given slightly different interpretations

29
Q

The first of two extra bits kept on the right during intermediate calculations of floating-point numbers; used to improve rounding accuracy.

A

Guard

30
Q

Method to make the intermediate floating-point result fit the floating-point format; the goal is typically to find the nearest number that can be represented in the format. It is also the name of the second of two extra bits kept on the right during intermediate floating-point calculations, which improves rounding accuracy.

A

Round

31
Q

The number of bits in error in the least significant bits of the significand between the actual number and the number that can be represented.

A

Units in the last place (ulp)

32
Q

A bit used in rounding in addition to guard and round that is set whenever there are nonzero bits to the right of the round bit.

A

Sticky bit

33
Q

Fused multiply add: A floating-point instruction that performs both a multiply and an add, but rounds only once after the add.

A

Fused multiply add

34
Q

Given that the parallelism occurs within a wide word, the extensions are classified as blank. It is also classified under the more general name of data level parallelism. They are known as well as vector or SIMD, for single instruction, multiple data (see COD Section 6.6 (Introduction to graphics processing units)).

A

subword parallelism

35
Q

ARMv8 added _____-bit registers to support subword parallelism.

A

128

36
Q

The add instruction, ADD, includes support for 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit numbers. Operands can be integers, but not blank

A

floating point numbers

37
Q

Number of assembly-language integer arithmetic and floating-point instructions in ARMv8

A

63

38
Q

Floating-point multiply instruction that produces a negative product

A

FNMUL

39
Q

Number of ARMv8 arithmetic core instructions

A

15

40
Q

Conditional compare that only compares if the initial condition is true

A

FCCMP

41
Q

ARMv8 has _____ assembly-language SIMD instructions.

A

245

42
Q

Which SIMD instruction version means the width of the elements in the destination register is twice the width of the elements in all source registers?

A

long

43
Q

Each SIMD version is denoted by a _____.

A

suffix

44
Q

The prefixes U, S, and F refer to _____

A

data types

45
Q

Wide means the width of the elements in the destination register and the first source registers is twice the width of the elements in the second source register.

A

Wide

46
Q

Blank means the width of the elements in the destination register is twice the width of the elements in all source registers.

A

Long

47
Q

Blank means the width of the elements in the destination register is half the width of the elements in all source registers.

A

Narrow

48
Q

IEEE 754 is a _____ for floating-point representation and computation.

A

standard

49
Q

The field of _____ examines how to solve mathematical problems using imprecision and limited representation of data.

A

numerical analysis

50
Q

A situation where an operation yields a number that is too small to represent with the fixed number of bits available is called _____.

A

underflow

Computer Architecture (6 decks)

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