Unit 5 Flashcards
1
Q
For every instruction, the first two steps are identical: Name them.
A
Send the program counter (PC) to the memory that contains the code and fetch the instruction from that memory.
Read one or two registers, using fields of the instruction to select the registers to read. For the LDUR and CBZ instructions, we need to read only one register, but most other instructions require reading two registers.
2
Q
3rd step for memory-reference instructions
A
Use ALU for address calculation
3
Q
3rd step for arithmetic-logic instructions
A
Use ALU for operation execution
4
Q
Every instruction must first be fetched from memory, based on the value of the blank.
A
program counter
5
Q
Every instruction reads one or two blank
A
registers
6
Q
3rd step for branch instructions
A
use ALU for comparison
7
Q
The blank stores the program that is to be executed.
A
instruction memory
8
Q
The blank stores the data needed by the running programs.
A
data memory
9
Q
The blank commands the datapath according to the instructions of the program by setting the control lines for each of the major functional units.
A
control unit
10
Q
The blank elements include the instruction and data memories, the register file, the ALU, and adders.
A
datapath
11
Q
An operational element, such as an AND gate or an ALU.
A
Combinational element
12
Q
A memory element, such as a register or a memory.
A
State element
13
Q
A blank element has at least two inputs and one output.
A
state
14
Q
The elements that operate on data values are all blank, which means that their outputs depend only on the current inputs.
A
combinational
15
Q
A sequential element is another name for a _____ element.
A
state
16
Q
A clock input is present on a _____ element.
A
state
17
Q
An ALU is a _____ element.
A
combinational
18
Q
The approach used to determine when data is valid and stable relative to the clock.
A
Clocking methodology
19
Q
A clocking scheme in which all state changes occur on a clock edge.
A
Edge-triggered clocking
20
Q
A signal used for multiplexor selection or for directing the operation of a functional unit; contrasts with a data signal, which contains information that is operated on by a functional unit.
A
Control signal
21
Q
The signal is logically high or true.
A
Asserted
22
Q
The signal is logically low or false.
A
Deasserted
23
Q
An blank allows us to read the contents of a register, send the value through some combinational logic, and write that register in the same clock cycle.
A
edge-triggered methodology
24
Q
For the 64-bit LEGv8 architecture, nearly all of these state and logic elements will have inputs and outputs that are blank, since that is the width of most of the data handled by the processor
A
64 bits wide
25
A rising clock edge refers to the clock changing from blank
0 to 1
26
A unit used to operate on or hold data within a processor. In the LEGv8 implementation, the blank include the instruction and data memories, the register file, the ALU, and adders.
Datapath element
27
The register containing the address of the instruction in the program being executed.
Program counter (PC)
28
To execute any instruction, we must start by blank.
fetching the instruction from memory
29
A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.
Register file
30
To increase the size of a data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item.
Sign-extend
31
There are two details in the definition of branch instructions (see COD Chapter 2 (Instructions: Language of the Computer)) to which we must pay attention:
The instruction set architecture specifies that the base for the branch address calculation is the address of the branch instruction.
The architecture also states that the offset field is shifted left 2 bits so that it is a word offset; this shift increases the effective range of the offset field by a factor of 4.
32
The address specified in a branch, which becomes the new program counter (PC) if the branch is taken. In the LEGv8 architecture, the blank is given by the sum of the offset field of the instruction and the address of the branch.
Branch target address
33
A branch where the branch condition is satisfied and the program counter (PC) becomes the branch target. All unconditional branches are taken branches.
Branch taken
34
A branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch.
Branch not taken or (untaken branch)
35
This simplest blank will attempt to execute all instructions in one clock cycle.
datapath
36
The normal case of fetching the next instruction memory requires blank, not PC + 1.
PC + 4,
37
The blank must be able to take inputs and generate a write signal for each state element, the selector control for each multiplexor, and the ALU control.
control unit
38
For load register and store register instructions, we use the ALU to compute the memory address by blank .
addition
39
For the R-type instructions, the ALU needs to perform one of the four actions (blank, blank, blank or blank), depending on the value of the 11-bit opcode field in the instruction (
AND, OR, subtract, or add
40
If the instruction is STUR, then ALUOp should be _____
00
41
If the instruction is STUR, then the ALU's four control inputs should be _____.
0010
42
For LDUR and STUR instructions, the ALU function _____.
the same
43
If the instruction is ORR, then ALUOp should be _____.
10
44
If the instruction is ORR, then as well as examining the ALUOp bits, the ALU control will also examine _____.
instruction's opcode field (Instruction[31:21])
45
If the instruction is ORR, then the ALU control will (after examining the ALUOp and opcode bits) output _____.
0001
46
From logic, a representation of a logical operation by listing all the values of the inputs and then in each case showing what the resulting outputs should be.
Truth table
47
An element of a logical function in which the output does not depend on the values of all the inputs. Don't-care terms may be specified in different ways.
Don't-care term
48
The blank, which as we saw in COD Chapter 2 (Instructions: Language of the computer), is between 6 and 11 bits wide and found in bits 31:26 to 31:21.
opcode field
49
The blank is always in bit positions 9:5 (Rn) for both R-type instructions and for the base register for load and store instructions.
first register operand
50
The blank is in one of two places. It is in bit positions 20:16 (Rm) for R-type instructions and it is in bit positions 4:0 (Rt) for the register to be written by load. That is also the field that specifies the register to be tested for zero for compare and branch on zero. Thus, we will need to add a multiplexor to select which field of the instruction is used to indicate the register number to be read.
other register operand
51
Another operand can also be a 19-bit offset for blank or a 9-bit offset for load and store.
compare and branch on zero
52
The blank for R-type instructions (Rd) and for loads (Rt) is in bit positions 4:0
destination register
53
The field that denotes the operation and format of an instruction.
Opcode
54
Also called single clock cycle implementation. An implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical.
Single-cycle implementation
55
In contrast, an unconditional branch instruction always branches, so the blank is not used.
ALU
56
An implementation technique in which multiple instructions are overlapped in execution, much like an assembly line.
Pipelining
57
.LEGv8 instructions classically take what five steps:
Fetch instruction from memory.
Read registers and decode the instruction.
Execute the operation or calculate an address.
Access an operand in data memory (if necessary).
Write the result into a register (if necessary).
58
When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute.
Structural hazard
59
Also called a pipeline data hazard. When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available.
Data hazard
60
Also called bypassing. A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory.
Forwarding
61
A specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction.
Load-use data hazard
62
Also called bubble. A stall initiated in order to resolve a hazard.
Pipeline stall
63
Also called branch hazard. When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected.
Control hazard
64
A method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from that assumption rather than waiting to ascertain the actual outcome.
Branch prediction
65
Blank increases the number of simultaneously executing instructions and the rate at which instructions are started and completed.
Pipelining
66
Pipelining does not reduce the time it takes to complete an individual instruction, also called the blank.
latency
67
Blank and blank help make a computer fast while still getting the right answers.
Branch prediction and forwarding
68
The number of stages in a pipeline or the number of stages between two instructions during execution.
Latency (pipeline)
69
The division of an instruction into five stages means a five-stage pipeline, which in turn means that up to five instructions will be in execution during any single clock cycle. Thus, we must separate the datapath into five pieces, with each piece named corresponding to a stage of instruction execution. Name them.
IF: Instruction fetch
ID: Instruction decode and register file read
EX: Execution or address calculation
MEM: Data memory access
WB: Write back
70
During instruction fetch, the next instruction is fetched from blank. The right half of IM is shaded to depict that the memory is read.
instruction memory (IM)
71
During instruction decode, the instruction's fields are converted into datapath control signals, and simultaneously the blank is read. For simplicity, just the register file is used to depict this stage. The right half is shaded to depict the read (vs. write).
register file (Reg)
72
During execute, the blank is used to perform the instruction's operation or to compute an address, or an adder is used for branches.
ALU
73
During data memory access, the blank may be read (for a load instruction) or written (for a store instruction). For load, the right half is shaded, indicating read. (For store, the left half would be shaded).
data memory (DM)
74
During write back, the blank may be written by certain instructions (like R-type instructions). The left half is shaded to indicate write (vs. read). Although two Reg icons appear in the stylized depictions, only one register file exists.
register file (Reg)
75
An instruction that does no operation to change state.
nop
76
Although the compiler generally relies upon the hardware to resolve hazards and thereby ensure correct execution, the compiler must understand the blank to achieve the best performance. Otherwise, unexpected stalls will reduce the performance of the compiled code.
pipeline
77
To discard instructions in a pipeline, usually due to an unexpected even
Flush
78
Prediction of branches at runtime using runtime information
Dynamic branch prediction
79
Also called branch history table. A small memory that is indexed by the lower portion of the address of the branch instruction and that contains one or more bits indicating whether the branch was recently taken or not.
Branch prediction buffer
80
A structure that caches the destination PC or destination instruction for a branch. It is usually organized as a cache with tags, making it more costly than a simple prediction buffer.
Branch target buffer
81
A branch predictor that combines local behavior of a particular branch and global information about the behavior of some recent number of executed branches.
Correlating predictor
82
A branch predictor with multiple predictions for each branch and a selection mechanism that chooses which predictor to enable for a given branch.
Tournament branch predictor
83
Also called interrupt. An unscheduled event that disrupts program execution; used to detect overflow.
Exception
84
An exception that comes from outside of the processor. (Some architectures use the term interrupt for all exceptions.)
Interrupt
85
An interrupt for which the address to which control is transferred is determined by the cause of the exception
Vectored interrupt
86
A 64-bit register used to hold the address of the affected instruction. (Such a register is needed even when exceptions are vectored.)
ELR
87
A register used to record the cause of the exception. In the LEGv8 architecture, this register is 32 bits, although some bits are currently unused. Assume there is a field that encodes the three possible exception sources mentioned above, with 8 representing an undefined instruction, 10 representing arithmetic overflow or underflow, and 12 representing hardware malfunction.
ESR
88
Also called imprecise exception. Interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause of the interrupt or exception.
Imprecise interrupt
89
Also called precise exception. An interrupt or exception that is always associated with the correct instruction in pipelined computers.
Precise interrupt
90
The parallelism among instructions.
Instruction-level parallelism
91
A scheme whereby multiple instructions are launched in one clock cycle
Multiple issue
92
An approach to implementing a multiple-issue processor where many decisions are made by the compiler before execution.
Static multiple issue
93
An approach to implementing a multiple-issue processor where many decisions are made during execution by the processor.
Dynamic multiple issue
94
Two primary and distinct responsibilities must be dealt with in a multiple-issue pipeline:
Packaging instructions into issue slots: how does the processor determine how many instructions and which instructions can be issued in a given clock cycle? In most static issue processors, this process is at least partially handled by the compiler; in dynamic issue designs, it is normally dealt with at runtime by the processor, although the compiler will often have already tried to help improve the issue rate by placing the instructions in a beneficial order.
Dealing with data and control hazards: in static issue processors, the compiler handles some or all of the consequences of data and control hazards statically. In contrast, most dynamic issue processors attempt to alleviate at least some classes of hazards using hardware techniques operating at execution time.
95
The positions from which instructions could issue in a given clock cycle; by analogy, these correspond to positions at the starting blocks for a sprint.
Issue slots
96
An approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions.
Speculation
97
The set of instructions that issues together in one clock cycle; the packet may be determined statically by the compiler or dynamically by the processor.
Issue packet
98
A style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields.
Very Long Instruction Word (VLIW)
99
Number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline.
Use latency
100
A technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together.
Loop unrolling
101
The renaming of registers by the compiler or hardware to remove antidependences.
Register renaming
102
Also called name dependence. An ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions.
Antidependence
103
An advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution.
Superscalar
104
Hardware support for reordering the order of instruction execution to avoid stalls.
Dynamic pipeline scheduling
105
The unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer-visible registers and memory.
Commit unit
106
A buffer within a functional unit that holds the operands and the operation.
Reservation station
107
The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register.
Reorder buffer
108
A situation in pipelined execution when an instruction blocked from executing does not cause the following instructions to wait.
Out-of-order execution
109
A commit in which the results of pipelined execution are written to the programmer visible state in the same order that instructions are fetched.
In-order commit
110
Both pipelining and multiple-issue execution increase peak instruction throughput and attempt to exploit blank.
instruction-level parallelism (ILP)
111
The organization of the processor, including the major functional units, their interconnection, and control.
Microarchitecture
112
The instruction set of visible registers of a processor; for example, in LEGv8, these are the 32 integer and 32 floating-point registers.
Architectural registers
113
Verilog can describe processors for simulation or with the intention that the Verilog specification be blank.
synthesized
114
The inherent execution time for an instruction.
Instruction latency
115
The first supercomputer.
CDC 6600
116
An approach that uses dynamic hazard detection, generalized forwarding, and reservation stations.
Tomasulo's algorithm
117
A computer that used a four-stage pipeline to overlap fetch, decode, and execute.
The IBM 7030, also known as Stretch,
118
The computer that introduced Tomasulo's algorithm.
IBM 360/91
119
Out-of-order instruction commits led to this unpopular situation.
imprecise interrupts
120
The original design for a superscalar processor was a two-issue machine called _________
Cheetah
121
_________ is a static multiple issue approach that was used in processors found in Cydrome and Multiflow mini-supercomputers.
VLIW
122
_________ is a more compiler-intensive approach to multiple issue that removed many VLIW drawbacks.
EPIC
123
_________ is an approach that uses aggressive loop unrolling and path prediction and has been used to exploit higher levels of ILP.
Trace scheduling
