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computer organization > the basics of logic design > Flashcards

the basics of logic design Flashcards

the basics of logic design

1
Q

electronics inside a modern computer are ___________

A

digital

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2
Q

digital electronics

A

operate with only two voltage levels of interest: high and low

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3
Q

signals are logically either:

A

asserted: true or 1
deasserted: false or 0

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4
Q

values 0 and 1 are

A

complements/inverses

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5
Q

combinational logic blocks

A

don’t contain memory
output: depends on the current input

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6
Q

logic blocks with memory

A

output: can depend on both the input and the state

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7
Q

state of the logic block

A

value stored in memory

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8
Q

logic block with n entries will have a truth table with ___ entries

A

2^n

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9
Q

OR operator

A

logical sum
A + B

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10
Q

AND operator

A

logical product
A · B

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11
Q

unary operator NOT

A

Ā

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12
Q

identity law

A

A + 0 = A and A · 1 = A

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13
Q

zero and one laws

A

A + 1 = 1 and A · 0 = 0

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14
Q

inverse laws

A

A + Ā = 1 and A · Ā = 0

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15
Q

commutative laws

A

A + B = B + A and A · B = B · A

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16
Q

associative laws

A

A + (B + C) = (A + B) + C and A · (B · C) = (A · B) · C

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17
Q

distributive laws

A

A · (B + C) = (A · B) + (A · C) and A + (B · C) = (A + B) · (A + C)

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18
Q

DeMorgan’s laws

A

(i) (A ∪ B)’ = A’ ∩ B’
(ii) (A ∩ B)’ = A’ ∪ B’

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19
Q

gates

A

implement basic logic functions

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20
Q

all logic functions can be constructed with only a single gate type, if that
gate is inverting

A
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21
Q

NOR and NAND gates

A

inverting gates

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22
Q

decoders

A

type of logic blocks used in building larger components

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23
Q

most common type of decoder

A

has an n-bit input and 2^n outputs, where only one output is asserted for each input combination

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24
Q

encoder

A

preforms the inverse function of a decoder

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25
Q

multiplexor

A

basic logic function
also called selectors because the output is one of the inputs selected by a control

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26
Q

multiplexor has __ inputs and they are:

A

3
two data values + selector

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27
Q

selector value

A

or control value
determines which of the inputs becomes the output

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28
Q

a multiplexor with n inputs will need ________ selector inputs

A

log…?

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29
Q

multiplexor consists of __ parts which are:

A

3
a decoder that generates n signals
an array of n AND gates
a single large OR gate

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30
Q

In a multiplexor, what is the purpose of the array of gates?

A

each gate combines one of the inputs with a signal from the decoder

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31
Q

In a multiplexor, what is the purpose of the OR gate?

A

incorporates the outputs of the AND gates

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32
Q

canonical form

A

every input is either true or a complemented variable, and there are only two levels of gates-AND and OR- with a possible inversion of the final output

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33
Q

two-level representation

A

logic function written in canonical form

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34
Q

types of two-level representation

A

sum of products: logical sum of products (terms using the AND operator)
product of sums: the opposite

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35
Q

only those truth table entries for which the function is true generate terms in the equation

A
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36
Q

we can use the relationship between a ___________ and a _____________
to generate a gate-level implementation of any set of logic functions

A

truth table
two-level representation

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37
Q

in a logic table each column represents a different ____________

A

logic function

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38
Q

programmable logic array (PLA)

A

a structured logic element composed of a set of inputs and corresponding input complements and two stages of logics

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39
Q

stages of logic in PLAs

A
  1. generates product terms of the inputs and input complements -> an array of AND gates that form a set of minterms
  2. generates sum terms of the product terms -> an array of OR gates, each of which forms a logical sum of any number of the product terms
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40
Q

minterms

A

a set of logic inputs joined by conjunction; the product terms from the first logic stage of the PLA; each product term can consist of any of the inputs or their complements

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41
Q

AND plane

A

size of the AND gate array

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42
Q

OR plane

A

size of the OR gate array

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43
Q

a row in the PLA corresponds to _______

A

each entry where the output is true, because it requires a product term

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44
Q

each output =

A

a potential row of OR gates in the second stage

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45
Q

the number of OR gates =

A

the number of truth table entries for which the output is true

46
Q

the total size of a PLA =

A

AND plane + OR plane

47
Q

PLA characteristics that make it an efficient way to implement a set of logic functions

A
  1. only the truth table entries that produce a true value for at least one output have any logic gates associated with them
  2. each different product term will have only one entry in the PLA, even if the product term is used in multiple outputs
48
Q

PALs

A

PLA-like structures that can be programmed when needed

49
Q

ROM

A

read-only memory
a memory whose contents are designated at creation time, after which contents can only be read

50
Q

How is ROM used?

A

as structured logic to implement a set of logic functions by using the terms in the logic functions as address inputs and the outputs as bits in each word of the memory

51
Q

Why is ROM called a memory?

A

it has a set of locations that can be read

52
Q

PROM

A

programmable ROM
it can be programmed when a designer knows its contents

53
Q

erasable PROMs

A

require a slow erasure process using UV light, and thus are used as read-only memories, except during the design and debugging process

54
Q

ROM height

A

number of addressable entries
2^m -> m input lines

55
Q

ROM width

A

the number of bits in each addressable entry = number of output bits

56
Q

the total number of bits in ROM=

A

height + width

57
Q

shape of the ROM

A

the height and the width

58
Q

a ROM can encode a collection of logic functions directly from the truth table

A
59
Q

if we have n functions with m inputs, we need a ROM with __ address lines and __ entries, with each entry being __ bits wide

A

m
2m
n

60
Q

the entries in the input portion of the truth table represent the addresses of the entries in the ROM, while the contents of the output portion of the truth table constitute the contents of the ROM

A
61
Q

a ROM is fully decoded means

A

it contains a full output word for every possible input combination

62
Q

as the number of inputs grows, the number of entries in the ROM …

A

grows exponentially

63
Q

advantage of PLAs

A

for real logical functions, the number of product terms grows much slower than exponentially

64
Q

advantage of ROMs

A

able to implement any logic function with the matching number of inputs and outputs => makes it easier to change if the function changes

65
Q

Why are small collections of gates preferred for small logic functions?

A

they have less overhead than ROM and PLA

66
Q

don’t cares

A

situations where we do not care what the value of the output is

67
Q

types of don’t cares

A

output and input

68
Q

output don’t cares

A

arise when we don’t care about the value of an output for some input combination
they appear as Xs in the output portion of the truth table

69
Q

input don’t cares

A

arise when an output depends on only some of the inputs
they appear as Xs in the input portion of the truth table

70
Q

Karnaugh maps

A

represent the truth table graphically, so that the product terms that may be combined are easily seen

71
Q

logic minimisation

A

critical to achieving efficient implementations
highly mechanical
can be preformed by design tools
the tools take advantage of the don’t cares

72
Q

array of logic elements

A

represented by showing that a given operation will happen to an entire collection of inputs

73
Q

bus

A

a collection of data lines that is treated together as a single logical signal

74
Q

What chooses the bus?

A

a multiplexor

75
Q

most buses are __ bits wide

A

32

76
Q

ALU

A

arithmetic logic unit
the brawn of the computer
device that performs the arithmetic operations or logical operations
a random number generator supplied with all computer systems

77
Q

1-bit ALU

A

the logical operations are easiest, because they map directly onto the hardware
components

78
Q

How does a 1- bit unit for AND and OR work?

A

multiplexor selects a AND b or a OR b, depending on whether the value of Operation is 0 or 1

79
Q

addition

A

an adder must have two inputs for the operands and a single-bit output for the sum

80
Q

full adder

A

or (3,2) adder
3 inputs, 2 outputs

81
Q

half-adder or

A

(2,2) adder

82
Q

32-bit ALU

A

created by connecting adjacent black boxes

83
Q

ripple carry adder

A

created by directly linking the carries of 1-bit adders

84
Q

slt

A
85
Q

clock

A

a free running signal with a fixed cycle time
clock frequency - inverse of the cycle time

86
Q

clock cycle

A

divided into two portions: high and low

87
Q

edge-triggered clocking

A

a clocking scheme in which all state changes occur on a clock edge
one clock edge is active and causes changes

88
Q

Why are state elements implemented with clocks?

A

so that the contents of the state elements only change on the active clock edge

89
Q

clocking methodology

A

the approach used to determine when data is valid and stable relative to the clock

90
Q

state elements

A

memory element

91
Q

How does a clock edge work?

A

it acts as a sampling signal, causing the value of the data input to a state element to be sampled and stored in the state element

92
Q

synchronous system

A

a memory system that employs clocks and where data signals are read only when the clocks indicates that the signal values are stable

93
Q

constraints in a clock system

A

the signals that are written into state elements must be valid when the active clock edge occurs

94
Q

When a signal valid?

A

when it is stable (not changing) and its value will not change again until the inputs change

95
Q

since combinational circuits cannot have feedback, if the inputs to a combinational logic unit are not changed, the outputs will eventually become valid

A
96
Q

How to ensure valid values on the active clock edges?

A

the clock must have a long enough period so that all the signals in the combinational logic block stabilise

97
Q

advantage of edge-triggering

A

it is possible to have a state element that is used as both an input and an output to the same block

98
Q

register files

A

a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed

99
Q

unlocked elements

A

simplest type of memory elements
don’t have a clock input
flip-flops, latches

100
Q

latch

A

a memory element in which the output is equal to the value of the stored state inside the element and the state is changed only on a clock edge

101
Q

flip-flops

A

a memory element in which the output is equal to the value of the stored state inside the element and the state is changed whenever the appropriate inputs change and the clock is asserted

102
Q

difference between latch and flip-flop

A

the point at which the clock causes the state to actually change
latch-whenever the appropriate inputs change
flip-flop-on a clock edge

103
Q

What the function of flip-flops and latches in computer applications?

A

to store a signal

104
Q

D flip-flop

A

a flip-flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs
has 2 input and 2 outputs

105
Q

outputs in a D flip-flop

A

the value of the internal state (Q) and its complement (|Q)

106
Q

inputs in a D flip-flop

A

the data b value to be stored (D) and a clock signal (C)

107
Q

What does the clock signal in a D flip-flop indicate?

A

when the latch should read the value on D and store it

108
Q

open latch

A

C is asserted => Q becomes D

109
Q

closed latch

A

C is deasserted => Q is whatever value was stored last

110
Q

transparent latch

A

when it’s open Q changes as D changes

111
Q

Are flip-flops transparent?

A

no, they change only on the edges

111
Q
A

computer organization (9 decks)

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