i/o Flashcards
Front Side Bus (FSB)
CPU to memory connection
Peripheral Component Interconnect Express (PCIe)
point-to-point
a bus has:
data lines: transmitting data
address lines: addressing/identifying device
control lines: send comands
bus protocol
a set of rules that needs to be followed by the connected devices for a successful data transfer
Devices are attached to a bus through an interface that has:
address decoder
data registers
status and control registers
a device has:
status registers: show the current status of the device
command registers: tell device to perform a certain task
data registers
vectored interrupts
interrupts with numbers
each device is assigned a unique interrupt number
IVT
interrupt vector table
interrupts vs. polling
interrupts: slow devices, ISR setup time < I/O servicing time
polling: high-speed devices
hybrid: start with interrupt, then switch to polling based on the load and speed of the device
maximum propagation delay
the amount of time required after an input signal is applied and has stabilised to the input of a circuit to the time that the output of the circuit has stabilised to the correct output signal
synchronous bus +/-
+ fast
- clock managment
asynchronous bus +/-
+ easy management with devices with different speeds
- longer handshake protocol :
1. master read
2. device ready
3. device done
4. master done
serial bus
simple to implement
different encoding can be used to synchronise clocks
preferred today
parallel bus
can transmit more data in a single cycle
maintaining clocking information and low interference on multiple links over a distance is a challenge
wider buses(multiple parallel bit lines)
+ more bandwidth
- expensive
