final dump

Question 1

UMA

Answer 1

same amount of memory for each processor
uniform(same) latency for memory accesses
large latency in a network with many processors and memory
crossbar interconnect used to connect processor and memory

Question 2

NUMA

Answer 2

local memory for each processor
low latency when accessing local memory

Question 3

temporal locality

Answer 3

When an information item, instruction or data is first needed, it should be brought back / kept close to the cache as it will likely be needed again

Question 4

spatial locality

Answer 4

Most time in programs is spent looping through the same block of instructions thus. Its useful to fetch several items located at adjacent address as they are likely to be used together

Question 5

fully associative cache

Answer 5

any data block anywhere
+ very flexible
- slow to search

Question 6

direct mapping

Answer 6

each memory block mapped to a specific cache block
+ fast to search
- inflexible

Question 7

n-way set-associative

Answer 7

n memory blocks in a set
+/- reasonably fast to search
+/- reasonably flexible

Question 8

LRU

Answer 8

cache keeps time stamps of accesses
replace least recently used block

Question 9

DMA

Answer 9

process of transferring data between main memory and hardware subsystem (i/o) without involvement of the processor

Question 10

cycle stealing

Answer 10

a method DMA applies to avoid competition on the memory bus between the CPU and the DMA engine

Question 11

DMA +/-

Answer 11

+ delivers high bulk data performance
+ frees CPU form doing bulk data transfers from device-> memory
- can interfere with CPU memory access
- extra intelligence (standalone chip) in devices to access memory

Question 12

DMA stages

Answer 12

1. CPU programs the DMA engine of the storage device
2. internal processing
3. DMA transfer from the device
4. interrupt to the CPU

Question 13

memory mapped io

Answer 13

uses same address space as to address both memory and i/o devices
memory address refers to portion of RAM or memory and registers of IO devices

Question 14

port mapped io

Answer 14

io devices mapped to separate address space
-> different set of signal lines to indicate a memory access vs a port access

Question 15

memory mapped io +/-

Answer 15

+ requires less internal logic -> cheaper
+ easier to build, faster, consumes less power and can be physically smaller
- address bus must be fully decoded for every device

Question 16

port mapped io +/-

Answer 16

+ less logic needed to decode discrete address and therefore costs less to add hardware to machine
- more instructions required to accomplish same task

Question 17

RISC

Answer 17

reduced instruction set computer
less and simpler instructions
emphasis on software
small code, high cycles
transistors used more for complex instructions
more power efficient
single word I
increases I per program, reduces CPI

Question 18

CISC

Answer 18

complex instruction set computer
lots of complex instructions
memory-to-memory operations
multiple word I
instructions may take multiple clock cycles
more energy hungry
increases CPI, reduces I per program

Question 19

ISA trade-offs

Answer 19

complexity, performance, energy use, security

Question 20

bubble

Answer 20

one clock cycle of idle time

Question 21

What recognises data dependencies?

Answer 21

control

Question 22

superscalar processors

Answer 22

CPU that implements a form of parallelism called instruction-level parallelism within a single processor
increased throughput
contain multiple execution units

Question 23

superscalar vs pipelining

Answer 23

multiple I executed in parallel using multiple I units
<->
multiple I executed in parallel by the same units dividing them into phases

Question 24

crossbar

Answer 24

network that provides a direct link between any pair of units connected to the network
-> used in UMA to connect processors
enables simultaneous transfers if target is not experiencing multiple requests

Question 25

switches formula

Answer 25

for n processors and k memory units,
n * k switches are needed

Question 26

MDR

Answer 26

CPU register that stores memory address of data that will be fetched to CPU or address to which data will be written

Question 27

MAR

Answer 27

CPU register that contains the data to be stored in main memory, or the fetched data from the memory

Question 28

given a memory cell of size x^a * z^b with y^c data pins

Answer 28

a=column bits
b-c=row bits

Question 29

flynn taxonomy

Answer 29

categorisation of forms of parallel computer architectures

Question 30

SIMD

Answer 30

single instruction multiple data
enables processing of multiple data with a single instruction
ex: retrieving multiple files at the same time, GPU, single-core superscalar processor
vector computers

Question 31

MIMD

Answer 31

employed to achieve parallelism
machines that use it have many asynchronous and independent processors
multiprocessors

Question 32

SISD

Answer 32

one instruction on a single data stream
ex: single-core CPU with pipelining
traditional Von Neumann

Question 33

MISD

Answer 33

multiple instructions on a single data stream

Question 34

SIMD <-> MIMD

Answer 34

SIMD: simpler, smaller, faster, operations can take longer
MIMD: capable of more complex operations, can perform complex operations concurently

Question 35

arbitration

Answer 35

process of resolving conflicts that arise when multiple devices attempt to access the bus at the same time
either using addresses, or first-come-first-service basis,
or a daisy chaining

Question 36

arbiter circuit

Answer 36

receives bus requests and processes them -> granted/denied
selects one request for bus access

Question 37

interrupts

Answer 37

a request for the processor to interrupt code that is currently executing so that an event can be processed

Question 38

interrupt service routine/handler (ISR)

Answer 38

function that can be executed when an interrupt is called

Question 39

interrupt cycle

Answer 39

1. device raises interrupt request
2. processor interrupts program execution
3. interrupts are disabled
4. device lowers interrupt
5. interrupt handled by interrupt handler
6. interrupt are enabled
7. execution of interrupted program is resumed

Question 40

thread

Answer 40

path of execution of a process
context: program counter, registers for the process

Question 41

process

Answer 41

program (instructions) + state (data)