Test #3 Flashcards

1
Q

Which of the following statements are TRUE about a microoperation? Select all that apply.

A fundamental operation on data stored in registers

Data transfer from one register to another is one category of microoperations

Subtraction may be a microoperation

Performed in one clock pulse

We considered three categories of microoperations

A

A fundamental operation on data stored in registers

Data transfer from one register to another is one category of microoperations

Subtraction may be a microoperation

Performed in one clock pulse

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2
Q

The notation:

R1 <- R2, R2 <- R1

indicates that Registers 1 and 2 swap their contents in one clock pulse

A

True

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3
Q

We can connect 8 registers, each register of which has 16 bits, to a common data bus as follows. Select all statements that are TRUE

May use multiplexers
Use size 16 x 1 MUXes
Need 8 MUXes
May use tri-state buffer gates
Would need 8 tri-state buffer gates for each data bus line

A

May use multiplexers
May use tri-state buffer gates
Would need 8 tri-state buffer gates for each data bus line

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4
Q

The output from a data bus created using MUXes can be loaded into multiple registers during one clock pulse

A

True

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5
Q

The following statement may be implemented as a microoperation:

A <- A + B

A

True

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6
Q

What special property of the Exclusive-OR gate did we discuss that allows us to build an adder-subtractor circuit as shown in Figure 4-7 (see below)?

A

If one input is one, the exclusive OR gate inverts the other input

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7
Q

The logical unit we studied in Figure 4-10 (see below) performs four different logical operations.

A

True

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8
Q

What do you get if your perform a logical left shift on the following bits?

11001010

10010101
00110010
10010100
01100101
00101000

A

10010100

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9
Q

If we perform a circular left shift on: 00101110 , the result is 01011100

A

True

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10
Q

If we perform an arithmetic right shift on: 10001101, the result is: 11000110

A

False

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11
Q

An arithmetic left-shift divides the binary number by 2

A

False

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12
Q

An arithmetic right-shift never produces overflow.

A

True

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13
Q

In the following microoperation:

p + q : R1 R2 + R3, R4 R5 R6

The ā€œvā€ symbol stands for the logical OR operation

A

True

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14
Q

Suppose the circuit of Figure 4-7 has the following input values.

M = 0

A = 0110

B = 0011

then the outputs are as follows:

S = 1001

C4 = 0

A

True

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15
Q

Suppose the circuit of Figure 4-7 has the following input values.

M = 1

A = 0110

B = 0011

then the outputs are as follows:

S = 0011

C4 = 1

A

True

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16
Q

Given Figure 4-9, determine what operation is performed on inputs A and B given the following values:

s1 = 0

s0 = 1

cin = 1

Subtraction
Increment A
Decrement A
Addition
Transfer A

A

Subtraction

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17
Q

Given Figure 4-9, determine what operation is performed on inputs A and B given the following values:

s1 = 1

s0 = 0

cin = 1

Subtraction
Increment A
Decrement A
Addition
Transfer A

A

Increment A

18
Q

Given Figure 4-9, determine what operation is performed on inputs A and B given the following values:

s1 = 1

s0 = 1

cin = 1

Subtraction
Increment A
Decrement A
Addition
Transfer A

A

Transfer A

19
Q

In Lab 6, we added two 2-bit numbers together using the 7483 4-bit adder chip. You could receive extra credit by adding two 4-bit numbers together.

20
Q

In Lab 7, we implemented the microoperation:

A <- A + B

using the following chips:

Two 7495 4-bit register chips

One 7483 adder chip

One 74157 MUX chip

21
Q

5 / 5 pts
We used four 2x1 multiplexers in Lab #7

22
Q

Given Figure 4-10 and the inputs below, what operation is sent out on the Ei output line?

S = 1

S = 1

Logical AND of two bits
Logical OR of two bits
Exclusive OR of two bits
Negation of B bit
None of these

A

None of these

23
Q

Given Figure 4-13 and the inputs below, what operation is sent out on F output line:

S = 0

S = 0

S = 1

S = 0

C = 1

Addition
Subtraction
Increment A
Decrement A
Transfer A

A

Increment A

24
Q

For the circuit in Figure 4-13 to perform a logical operation, the control lines must equal 11

25
Let A = 10100011 and let B (the control) = 00001111. What is the result of the selective-complement operation on A and B? 10101111 10101100 10100000 00000011 11110011
10101100
26
In Lab #7, how many times do we have to pulse the clock in order to get the values fom the switches into registers A and B, have the values A and B added together, and then the sum of A and B loaded into register A? 0 1 2 3 None of these
2
27
The purpose of the MUXes in Lab #7 is to select where the value to be loaded into Register A comes from
True
28
Each machine instruction for a particular CPU is made up of exactly one microoperation
True
29
An arithmetic shift right corresponds to a multiplication by 2
False
30
The binary number below is written using 2's complement notation. What decimal number does it represent? 10011011 155 -430 101 -101 -28
-101
31
Three-state TTL chips have three possible outputs: logical 0, logical 1, and high-impedance
True
32
A bus system for 8 registers, each containing 16 bits, may be constructed using three-state buffer gates together with 2 x 4 decoders.
False
33
Given the 8-bit binary number: 11111100 Suppose this binary number represents a signed binary number (the left-most bit is a sign bit). What is the decimal number representation of the above number? 4 -2 -4 -6 -8
-4
34
The result of the following subtraction operation is what? Assume signed numbers. 1101 - 0010 1100 0011 0110 1011
1011
35
In Lab #6, we saw that the 7483 adder chip does not have its ground and power pins in the standard locations
True
36
The selective-clear logical operation is shown below: A: 1000 0001 B: 1111 0000 (Mask) Results : 1111 0001
False
37
In Lab #6, what did we have to do with the carry-input to the 4-bit adder? Ignore it Set to -1 Set to 1 Set to 0 None of these
Set to 0
38
The selective-set logical operation is implemented with AND gates
False
39
The selective-complement logical operaion is implemented with exclusive OR gates
True
40
The 2's complement of 0110 1100 is: 1110 0011True 1100 0011 1001 1011 1001 1100 1001 0100
10010100