Test #3

Question 1

Which of the following statements are TRUE about a microoperation? Select all that apply.

A fundamental operation on data stored in registers

Data transfer from one register to another is one category of microoperations

Subtraction may be a microoperation

Performed in one clock pulse

We considered three categories of microoperations

Answer 1

A fundamental operation on data stored in registers

Data transfer from one register to another is one category of microoperations

Subtraction may be a microoperation

Performed in one clock pulse

Question 2

The notation:

R1 <- R2, R2 <- R1

indicates that Registers 1 and 2 swap their contents in one clock pulse

Answer 2

True

Question 3

We can connect 8 registers, each register of which has 16 bits, to a common data bus as follows. Select all statements that are TRUE

May use multiplexers
Use size 16 x 1 MUXes
Need 8 MUXes
May use tri-state buffer gates
Would need 8 tri-state buffer gates for each data bus line

Answer 3

May use multiplexers
May use tri-state buffer gates
Would need 8 tri-state buffer gates for each data bus line

Question 4

The output from a data bus created using MUXes can be loaded into multiple registers during one clock pulse

Answer 4

True

Question 5

The following statement may be implemented as a microoperation:

A <- A + B

Answer 5

True

Question 6

What special property of the Exclusive-OR gate did we discuss that allows us to build an adder-subtractor circuit as shown in Figure 4-7 (see below)?

Answer 6

If one input is one, the exclusive OR gate inverts the other input

Question 7

The logical unit we studied in Figure 4-10 (see below) performs four different logical operations.

Answer 7

True

Question 8

What do you get if your perform a logical left shift on the following bits?

11001010

10010101
00110010
10010100
01100101
00101000

Answer 8

10010100

Question 9

If we perform a circular left shift on: 00101110 , the result is 01011100

Answer 9

True

Question 10

If we perform an arithmetic right shift on: 10001101, the result is: 11000110

Answer 10

False

Question 11

An arithmetic left-shift divides the binary number by 2

Answer 11

False

Question 12

An arithmetic right-shift never produces overflow.

Answer 12

True

Question 13

In the following microoperation:

p + q : R1 R2 + R3, R4 R5 R6

The “v” symbol stands for the logical OR operation

Answer 13

True

Question 14

Suppose the circuit of Figure 4-7 has the following input values.

M = 0

A = 0110

B = 0011

then the outputs are as follows:

S = 1001

C4 = 0

Answer 14

True

Question 15

Suppose the circuit of Figure 4-7 has the following input values.

M = 1

A = 0110

B = 0011

then the outputs are as follows:

S = 0011

C4 = 1

Answer 15

True

Question 16

Given Figure 4-9, determine what operation is performed on inputs A and B given the following values:

s1 = 0

s0 = 1

cin = 1

Subtraction
Increment A
Decrement A
Addition
Transfer A

Answer 16

Subtraction

Question 17

Given Figure 4-9, determine what operation is performed on inputs A and B given the following values:

s1 = 1

s0 = 0

cin = 1

Subtraction
Increment A
Decrement A
Addition
Transfer A

Answer 17

Increment A

Question 18

Given Figure 4-9, determine what operation is performed on inputs A and B given the following values:

s1 = 1

s0 = 1

cin = 1

Subtraction
Increment A
Decrement A
Addition
Transfer A

Answer 18

Transfer A

Question 19

In Lab 6, we added two 2-bit numbers together using the 7483 4-bit adder chip. You could receive extra credit by adding two 4-bit numbers together.

Answer 19

True

Question 20

In Lab 7, we implemented the microoperation:

A <- A + B

using the following chips:

Two 7495 4-bit register chips

One 7483 adder chip

One 74157 MUX chip

Answer 20

True

Question 21

5 / 5 pts
We used four 2x1 multiplexers in Lab #7

Answer 21

True

Question 22

Given Figure 4-10 and the inputs below, what operation is sent out on the Ei output line?

S = 1

S = 1

Logical AND of two bits
Logical OR of two bits
Exclusive OR of two bits
Negation of B bit
None of these

Answer 22

None of these

Question 23

Given Figure 4-13 and the inputs below, what operation is sent out on F output line:

S = 0

S = 0

S = 1

S = 0

C = 1

Addition
Subtraction
Increment A
Decrement A
Transfer A

Answer 23

Increment A

Question 24

For the circuit in Figure 4-13 to perform a logical operation, the control lines must equal 11

Answer 24

False

Question 25

Let A = 10100011 and let B (the control) = 00001111.

What is the result of the selective-complement operation on A and B?

10101111
10101100
10100000
00000011
11110011

Answer 25

10101100

Question 26

In Lab #7, how many times do we have to pulse the clock in order to get the values fom the switches into registers A and B, have the values A and B added together, and then the sum of A and B loaded into register A?

0
1
2
3
None of these

Answer 26

2

Question 27

The purpose of the MUXes in Lab #7 is to select where the value to be loaded into Register A comes from

Answer 27

True

Question 28

Each machine instruction for a particular CPU is made up of exactly one microoperation

Answer 28

True

Question 29

An arithmetic shift right corresponds to a multiplication by 2

Answer 29

False

Question 30

The binary number below is written using 2’s complement notation.

What decimal number does it represent?

10011011

155
-430
101
-101
-28

Answer 30

-101

Question 31

Three-state TTL chips have three possible outputs:

logical 0, logical 1, and high-impedance

Answer 31

True

Question 32

A bus system for 8 registers, each containing 16 bits, may be constructed using three-state buffer gates together with 2 x 4 decoders.

Answer 32

False

Question 33

Given the 8-bit binary number: 11111100

Suppose this binary number represents a signed binary number (the left-most bit is a sign bit).

What is the decimal number representation of the above number?

4
-2
-4
-6
-8

Answer 33

-4

Question 34

The result of the following subtraction operation is what? Assume signed numbers.

1101  -  0010

1100
0011
0110
1011

Answer 34

1011

Question 35

In Lab #6, we saw that the 7483 adder chip does not have its ground and power pins in the standard locations

Answer 35

True

Question 36

The selective-clear logical operation is shown below:

A: 1000 0001

B: 1111 0000 (Mask)

Results : 1111 0001

Answer 36

False

Question 37

In Lab #6, what did we have to do with the carry-input to the 4-bit adder?

Ignore it
Set to -1
Set to 1
Set to 0
None of these

Answer 37

Set to 0

Question 38

The selective-set logical operation is implemented with AND gates

Answer 38

False

Question 39

The selective-complement logical operaion is implemented with exclusive OR gates

Answer 39

True

Question 40

The 2’s complement of 0110 1100 is:
1110 0011True
1100 0011
1001 1011
1001 1100
1001 0100

Answer 40

10010100