Test #2

Question 1

Both RAM and ROM are considered to be volatile

Answer 1

False

Question 2

How many address lines does a 4096 x 16 RAM chip have?

6
8
10
12
None of these

Answer 2

12

Question 3

What is the maximum number of bytes of data that can be stored in a 4096 x 16 RAM?

1024
2048
4096
8192
None of these

Answer 3

8192

Question 4

The contents of the 2716 EPROM chip is erased by using ultrviolet light

Answer 4

True

Question 5

The figures of the first registers that we considered in class were built from D flip-flops

Answer 5

True

Question 6

An encoder was used in the construction of a 4 x 3 RAM circuit shown in class

Answer 6

False

Question 7

An 8x1 multiplexer has how many select lines?
1
2
3
4
5

Answer 7

3

Question 8

In Lab #5, we saw that the basic clocked SR latch changes state on the falling edge of the clock.

Answer 8

False

Question 9

A JK flip-flop can be easily turned into a D flip-flop using a single AND gate.

Answer 9

False

Question 10

The SR flip-flop and the JK flip-flop are very similar in their operation except that the JK flip-flop does not allow both J and K inputs to be 1 at the same time.

Answer 10

False

Question 11

An 4x2 encoder and a 2x4 decoder are considered to be inverses of each other.

Answer 11

True

Question 12

A 4x1 Multiplexer connects one of it’s four input lines to the output line.

Answer 12

True

Question 13

A 1x8 demultiplexer has two select lines.

Answer 13

False

Question 14

The Boolean function F(A,B,C) = m(0, 1, 5, 6) may be implemented using a 8x1 or a 4x1 Mux.

Answer 14

True

Question 15

A single flip-flop is capable of storing 4 bits of data at any given time.

Answer 15

False

Question 16

For the SR flip-flop, if S=1 and R=0, then this flip-flop will be cleared at the next clock pulse.

Answer 16

False

Question 17

All flip-flops require a clock input in order to operate.

Answer 17

True

Question 18

The excitation table for the JK flip-flop is as follows:

Q(t) Q(t+1) | J K

0 0 | x 0

0 1 | x 1

1 0 | 1 x

1 1 | 0 x

Answer 18

False

Question 19

A JK flip-flop can be easily converted to a D flip=flop by tying the J and K inputs directly to each other.

Answer 19

False

Question 20

There are two types of shift registers: a right shift or a left shift register.

Answer 20

True

Question 21

A master-slave SR flip-flop changes state on the falling edge of the clock as seen in Lab #5.

Answer 21

False

Question 22

A sequential circuit contains one or more flip-flops.

Answer 22

True

Question 23

The state diagram of a sequential circuit shows what states the circuit goes through as well as the order in which the states occur.

Answer 23

True

Question 24

The design process for a sequential circuit is a 4-step process that involves the following steps in the order shown:

1. Draw state diagram
2. Develop the K-maps
3. Generate the transition table
4. Draw the sequential circuit

Answer 24

False

Question 25

There is a pattern in the count sequence of a 3-bit count-up counter that makes the design of this circuit easy. So easy, in fact, that you don’t have to go through the four step design process.

Answer 25

True

Question 26

It is possible to design a sequential circuit that goes through the count sequence:

1, 5, 3, 7, and then repeats

Answer 26

True

Question 27

The register in (Figure 2-6) has no way to control when a value is loaded into the register.

Answer 27

True

Question 28

The register in (figure 2-9) has which of the following capabilities? Select all that apply.

Shift down
Shift up
Add 1 to the register
Load new bits into register
Keep same value

Answer 28

Shift down
Shift up
Load new bits into register
Keep same value

Question 29

Don’t care conditions associated with a Boolean function may or may not be used as 1’s when simplifying the K-map

Answer 29

True

Question 30

In Lab #4, you built a 2-bit binary counter that counts up as long a the external input y is 1. When y = 0, the counter remains in its current state.

Answer 30

True

Question 31

In Lab #5, you built a clocked SR latch. The extra credit part involved putting two clocked SR latches together to build an SR master-slave flip-flop

Answer 31

True

Question 32

If we design a sequential circuit that counts: 0, 1, 2, 4, 5, 7,… and then repeats,

we will obtain the following equations:

J(C) = B K(C) = B

J(B) = A K(B) = 1

J(A) = 1 K(A) = 1

Answer 32

False

Question 33

If the sequential circuit in Problem #32 boots into state 6, what is the next state that will occur?

0
1
2
3
4
5

Answer 33

0