Test #2 Flashcards
(33 cards)
Both RAM and ROM are considered to be volatile
False
How many address lines does a 4096 x 16 RAM chip have?
6
8
10
12
None of these
12
What is the maximum number of bytes of data that can be stored in a 4096 x 16 RAM?
1024
2048
4096
8192
None of these
8192
The contents of the 2716 EPROM chip is erased by using ultrviolet light
True
The figures of the first registers that we considered in class were built from D flip-flops
True
An encoder was used in the construction of a 4 x 3 RAM circuit shown in class
False
An 8x1 multiplexer has how many select lines?
1
2
3
4
5
3
In Lab #5, we saw that the basic clocked SR latch changes state on the falling edge of the clock.
False
A JK flip-flop can be easily turned into a D flip-flop using a single AND gate.
False
The SR flip-flop and the JK flip-flop are very similar in their operation except that the JK flip-flop does not allow both J and K inputs to be 1 at the same time.
False
An 4x2 encoder and a 2x4 decoder are considered to be inverses of each other.
True
A 4x1 Multiplexer connects one of it’s four input lines to the output line.
True
A 1x8 demultiplexer has two select lines.
False
The Boolean function F(A,B,C) = m(0, 1, 5, 6) may be implemented using a 8x1 or a 4x1 Mux.
True
A single flip-flop is capable of storing 4 bits of data at any given time.
False
For the SR flip-flop, if S=1 and R=0, then this flip-flop will be cleared at the next clock pulse.
False
All flip-flops require a clock input in order to operate.
True
The excitation table for the JK flip-flop is as follows:
Q(t) Q(t+1) | J K
0 0 | x 0
0 1 | x 1
1 0 | 1 x
1 1 | 0 x
False
A JK flip-flop can be easily converted to a D flip=flop by tying the J and K inputs directly to each other.
False
There are two types of shift registers: a right shift or a left shift register.
True
A master-slave SR flip-flop changes state on the falling edge of the clock as seen in Lab #5.
False
A sequential circuit contains one or more flip-flops.
True
The state diagram of a sequential circuit shows what states the circuit goes through as well as the order in which the states occur.
True
The design process for a sequential circuit is a 4-step process that involves the following steps in the order shown:
- Draw state diagram
- Develop the K-maps
- Generate the transition table
- Draw the sequential circuit
False