Test #2 Flashcards

(33 cards)

1
Q

Both RAM and ROM are considered to be volatile

A

False

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2
Q

How many address lines does a 4096 x 16 RAM chip have?

6
8
10
12
None of these

A

12

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3
Q

What is the maximum number of bytes of data that can be stored in a 4096 x 16 RAM?

1024
2048
4096
8192
None of these

A

8192

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4
Q

The contents of the 2716 EPROM chip is erased by using ultrviolet light

A

True

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5
Q

The figures of the first registers that we considered in class were built from D flip-flops

A

True

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6
Q

An encoder was used in the construction of a 4 x 3 RAM circuit shown in class

A

False

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7
Q

An 8x1 multiplexer has how many select lines?
1
2
3
4
5

A

3

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8
Q

In Lab #5, we saw that the basic clocked SR latch changes state on the falling edge of the clock.

A

False

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9
Q

A JK flip-flop can be easily turned into a D flip-flop using a single AND gate.

A

False

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10
Q

The SR flip-flop and the JK flip-flop are very similar in their operation except that the JK flip-flop does not allow both J and K inputs to be 1 at the same time.

A

False

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11
Q

An 4x2 encoder and a 2x4 decoder are considered to be inverses of each other.

A

True

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12
Q

A 4x1 Multiplexer connects one of it’s four input lines to the output line.

A

True

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13
Q

A 1x8 demultiplexer has two select lines.

A

False

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14
Q

The Boolean function F(A,B,C) = m(0, 1, 5, 6) may be implemented using a 8x1 or a 4x1 Mux.

A

True

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15
Q

A single flip-flop is capable of storing 4 bits of data at any given time.

A

False

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16
Q

For the SR flip-flop, if S=1 and R=0, then this flip-flop will be cleared at the next clock pulse.

17
Q

All flip-flops require a clock input in order to operate.

18
Q

The excitation table for the JK flip-flop is as follows:

Q(t) Q(t+1) | J K

0 0 | x 0

0 1 | x 1

1 0 | 1 x

1 1 | 0 x

19
Q

A JK flip-flop can be easily converted to a D flip=flop by tying the J and K inputs directly to each other.

20
Q

There are two types of shift registers: a right shift or a left shift register.

21
Q

A master-slave SR flip-flop changes state on the falling edge of the clock as seen in Lab #5.

22
Q

A sequential circuit contains one or more flip-flops.

23
Q

The state diagram of a sequential circuit shows what states the circuit goes through as well as the order in which the states occur.

24
Q

The design process for a sequential circuit is a 4-step process that involves the following steps in the order shown:

  1. Draw state diagram
  2. Develop the K-maps
  3. Generate the transition table
  4. Draw the sequential circuit
25
There is a pattern in the count sequence of a 3-bit count-up counter that makes the design of this circuit easy. So easy, in fact, that you don't have to go through the four step design process.
True
26
It is possible to design a sequential circuit that goes through the count sequence: 1, 5, 3, 7, and then repeats
True
27
The register in (Figure 2-6) has no way to control when a value is loaded into the register.
True
28
The register in (figure 2-9) has which of the following capabilities? Select all that apply. Shift down Shift up Add 1 to the register Load new bits into register Keep same value
Shift down Shift up Load new bits into register Keep same value
29
Don't care conditions associated with a Boolean function may or may not be used as 1's when simplifying the K-map
True
30
In Lab #4, you built a 2-bit binary counter that counts up as long a the external input y is 1. When y = 0, the counter remains in its current state.
True
31
In Lab #5, you built a clocked SR latch. The extra credit part involved putting two clocked SR latches together to build an SR master-slave flip-flop
True
32
If we design a sequential circuit that counts: 0, 1, 2, 4, 5, 7,... and then repeats, we will obtain the following equations: J(C) = B K(C) = B J(B) = A K(B) = 1 J(A) = 1 K(A) = 1
False
33
If the sequential circuit in Problem #32 boots into state 6, what is the next state that will occur? 0 1 2 3 4 5
0