SYNCHRONOUS SEQUENTIAL LOGIC II Flashcards
Describe state equations and give examples
A state equation is an algebraic expression that specifies the condition for a flip-flop state transition.
(t+1) denotes the next state of the flip-flop one clock edge later.
The right side of the equation is Boolean expression that specifies the present state and input conditions that make the next state equal to 1.
A state equation (transition equation) specifies the next state as a function of the present state and inputs.
*See page 35 and 36 for equations
Describe the state table and give examples
The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table (sometimes called transition table).
A sequential circuit with m flipflops and n inputs needs 2 ^m+n rows in the state table.
*See page 37 and 39
Describe the state diagram and give examples
A state diagram is used to graphically represent the
information available in a state table
- A state is represented by a circle
- The transitions between states are indicated by directed lines connecting the circles.
*See page 38 and 39
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
https://upscfever.com/upsc-fever/en/gatecse/en-gatecse-chp26.html#:~:text=Analysis%20with%20D%20Flip%2DFlops,output%20of%20the%20flip%2Dflop.
Describe an FSM and give an example of one
FSM is a reactive system whose response to a particular stimulus (a signal, or a piece of input) is not the same on every occasion, depending on its current “state”.
A synchronous sequential circuit is also called as Finite State Machine(FSM), if it has finite number of states.
For example: A parking ticket machine
A Parking ticket machine will not print a ticket when you press the button unless you have already inserted some money.
Thus the response to the print button depends on the previous history of the use of the system.
Explain different types of FSM
Mealy
- The output is a function of both the present state and input.
- Referred to as a Mealy FSM or Mealy machine.
Moore
- The output is a function of the present state only.
- Referred to as a Moore FSM or Moore machine.
They only differ in the way the output is generated.
Describe the mealy machine and illustrate its circuits, state diagram and state table
The outputs will be valid only at positive (or negative) transition of the clock signal.
The number of states required in Mealy state machine is less than or equal to the number of states required in Moore state machine.
*See page 51 and 52
Give the 6 tuple description of the mealy and moore machines
Q is a finite set of states.
∑ is a finite set of symbols called the input alphabet.
O is a finite set of symbols called the output alphabet.
δ is the input transition function where δ: Q × ∑ → Q
X is the output transition function where X: Q × ∑ → O
q0 is the initial state from where any input is processed (q0 ∈ Q).
Describe the moore machine and illustrate its circuits, state diagram and state table
The outputs of the sequential circuit are synchronized with the clock, because they depend only on flip-flop outputs that are synchronized with the clock.
The number of states required in Moore state machine is more than or equal to the number of states required in Mealy state machine.
*See page 53 and 55
Give the differences between the mealy and moore machines
-Output
Mealy- Depends both upon the present state and the present input
Moore- Depends only upon the present state.
-No. of States
Mealy generally has fewer states than Moore Machine.
-Output Function
Mealy- The value of the output function is a function of the transitions and the changes, when the input logic on
the present state is done.
Moore- The value of the output function is a function of the current state and the changes at the clock edges, whenever state changes occur.
-Speed
Mealy machines react faster to inputs. They generally react in the same clock cycle.
In Moore machines, more logic is required to decode the outputs resulting in more circuit delays. They generally react one clock cycle later.
Give some Distinguishing characteristics of a computer
Memory size - the number of storage bits in the computer
Processor clock speed
List the different timing issues considered for: Flip-Flops, Combinational circuits and sequential circuits
For Flip-flops:
- Set-up time
- Hold time
- Propagation delay
For Combinational circuits:
- Contamination delay
- Propagation delay
For Sequential circuits:
- Clock frequency / Clock cycle time
Describe the ideal characteristics for a clock signal. Illustrate a clock period
Minimum clock period: Tmin
Maximum clock frequency: fmax
*See page 57
Define and illustrate, using a waveform, propagation delay
The amount of time needed for a change in a logic input to result in a permanent change at an output.
New output value is guaranteed to be valid after a
time period equal to the propagation delay, tpd
The output is guaranteed to be stable with the new value
after the propagation delay
*See page 58 and 59 and 60
Define and illustrate, using a waveform, contamination delay
The amount of time needed for a change in a logic input to result in an initial change at an output
New output remains unchanged for a time period equal
to the contamination delay, tcd
The output is guaranteed to be stable with old value
until the contamination delay
*See page 58 and 59 and 60
How does one calculate propagation and contamination timings in complex circuits
Propagation delays are additive
Locate the longest combination of tpd
Contamination delays may not be additive
Locate the shortest path of tcd
*See page 62 for example
What are the Timing Parameters for Sequential Logic
Propagation delay (tClk−Q) - The amount of time needed for a change in the flip flop-clock input (e.g. rising edge) to result in a permanent change at the flip-flop output (Q).
Contamination delay (tcd) - The amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q).
Setup time (ts) - The amount of time before the clock edge that data input D must be stable.
Hold time (th) – The amount of time after the clock edge that data input D must be held stable.
What are the restrictions in the D Flip Flop in terms of setup and hold times and why are they set
D input must be valid at least ts (setup time) before the rising clock edge
D input must be held steady th (hold time) after rising clock edge
These restrictions Limit the maximum clock frequency the circuit can operate
Violation of these restrictions leads to Improper circuit operation
*See page 67
Describe and illustrate the contamination and propagation delay of sequential logic circuits
Output unchanged for a time period equal to the contamination delay, tcd after the rising clock edge
New output guaranteed valid after time equal to the propagation delay, tClk-Q
Follows rising clock edge
*See page 66 for illustration
Illustrate the timings of an edge-triggered flip flop
*See page 68
Describe and illustrate clock skew and jitter
Clock skew
- Spatial variation in temporally equivalent clock edges;
deterministic + random, tSK
Clock jitter
- Temporal variations in consecutive edges of the clock signal; modulation + random noise
- Cycle-to-cycle (short-term) tJS
- Long term tJL
Both skew and jitter affect the effective cycle time
Only skew affects the race margin
*See page 79
What is the importance of the pulse width
Important for level sensitive clocking
DO the qs from page 79 to the end
