SYNCHRONOUS SEQUENTIAL LOGIC

Question 1

What are the different types of sequential circuits

Answer 1

Synchronous
Asynchronous

Question 2

Define and illustrate a sequential circuit and memory elements

Answer 2

 A sequential circuit is specified by a time sequence of
inputs, outputs, and internal states .

 Memory elements are digital circuits that can store and retrieve data in the form of 1’s and 0’s.

*See page 2

Question 3

Describe synchronous sequential circuits

Answer 3

 Circuit output changes only at some discrete instants of time.
-It achieves synchronization by using a timing signal called the clock.
-One input is a clock
-On the clock the next state becomes the present state of the system.

 The memory elements are affected only at discrete instants of time
-Memory elements are affected only with the arrival of a clock pulse

Question 4

Describe asynchronous sequential circuits

Answer 4

 The circuit behavior is determined by the signals at any instant of time
-Circuit output can change at any time (clockless).
-It is also affected by the order the inputs change

Question 5

When is a circuit called a clocked sequential circuit?

Answer 5

-If memory elements use clock pulses in their inputs, the circuit is called Clocked sequential circuit

Question 6

Define: inputs, outputs, presentState, and NextState

Answer 6

 Inputs – All the outside logic signal inputs to the circuit. Typically, the clock is not consider part of the signal inputs of the circuit.

 Outputs – The logic signal outputs.

 Present State – the logic value of all the state variables of the system. These are stored in the state memory.

 Next State – Given the present state and the current values on the inputs, the next state represents the next logic state the circuit will transition to on the next clock.

Question 7

Describe a flipflop

Answer 7

 Flipflops - Storage elements (memory) used
-A flip-flop is a binary storage device capable of storing one bit of information.
-Output = either 0 or 1.

Question 8

Describe and illustrate the Synchronous Clocked Sequential Circuit

Answer 8

 The flip-flops receive their inputs from the
combinational circuit and also from a clock signal
with pulses that occur at fixed intervals of time, as
shown in the timing diagram.
-The transition from one state to the next occurs only at
predetermined intervals dictated by the clock pulses.

*See page 5

Question 9

Define latches and flipflops

Answer 9

 Latches - Storage elements that operate with signal levels (rather than signal transitions)
- Level sensitive devices

 Flipflops - Storage elements that are controlled by a
clock transition
- Edge-sensitive devices.

Question 10

Describe SR Latch and illustrate its circuits and truth table

Answer 10

 The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates.
-It has two inputs labeled S for set and R for reset.
-Bistable latch – Remembers output until input changes its output
-Outputs are cross-coupled
-Active high – Q is always 1 at the original state

*See page 7 and 10

Question 11

Draw a simulation of a waveform of the SR Latch

Answer 11

*See page 8

Question 12

Describe the SR implementation using NAND gates and draw the truth table and circuits

Answer 12

 Active low – Q is always 0 at the original state
 The input signals for the NAND require the complement of those values used for the NOR latch.

*See page 9 and 10

Question 13

Describe and illustrate the SR Latch with Control Input (SR)’- (implementation using both NOR and NAND gates

Answer 13

 The operation of the basic SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed.
 It consists of the basic SR latch and two additional NAND gates.
 The outputs of the NAND gates stay at the logic-1 level as long as the enable signal remains at 0.

*See page 11-14

Question 14

Describe and illustrate the D Latch (Transparent Latch)

Answer 14

-One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time.
-The D input is sampled when En = 1. If D = 1, the Q output goes to 1, placing the circuit in the set state. If D = 0, output Q goes to 0, placing the circuit in the reset state.

*See page 15-16

Question 15

Illustrate the graphic symbols for latches

Answer 15

 A latch is designated by a rectangular block with inputs on the left and outputs on the right.
 One output designates the normal output, and the other designates the complement output.
 In a NAND gate latch, bubbles are added to the inputs to indicate that setting and resetting occur with a logic-0 signal.

*See page 17

Question 16

Describe the synchronization problems involved with using latches and the possible solution

Answer 16

 Latches are “transparent” (= any change on the inputs is seen at the outputs immediately).
-This causes synchronization problems.
-Solution: use latches to create flip-flops that can respond (update) only on specific times (instead of any time).

 The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger, and the transition it causes is said to trigger the flip-flop.

Question 17

Give examples of types of flip-flops

Answer 17

-D flip-flop
-JK flip-flop
-T flip-flop,

Question 18

Describe and illustrate Clock Response in Flip-Flop

Answer 18

The key to the proper operation of a flip-flop is to trigger
it only during a signal transition .

*See page 19

Question 19

Describe and illustrate the edge-triggered D Flip-flop

Answer 19

-The first latch is called the master and the second the
slave.
-The circuit samples the D input and changes its output Q only at the negative-edge of the controlling clock.
-A change in the output of the flip-flop can be triggered only by and during the transition of the clock from 1 to 0.

*See page 20 and 21 for the illustration

Question 20

Illustrate the combination of the gated D latch and the Gated SR Latch together with its wave form

Answer 20

*See page 22 and 23

Question 21

Describe and illustrate the D-Type Positive-Edge-Triggered Flip-Flop

Answer 21

Another more efficient construction of an edge-triggered D flip-flop uses three SR latches.
 Two latches respond to the external D(data) and CLK(clock) inputs.
 The third latch provides the outputs for the flip-flop.
The S and R inputs of the output latch are maintained at the logic-1 level when Clk = 0. This causes the output to remain in its present state.

*See page 24 and 25

Question 22

Describe the JK Flip-Flop and illustrate its symbols, circuit diagram and truth table

Answer 22

 There are three operations that can be performed with a flip-flop: set it to 1, reset it to 0, or complement its output.

 The JK flip-flop performs all three operations. The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates.

*See page 26
*S

Question 23

Describe the functioning of the JK Flip-flop

Answer 23

*See page 27

Question 24

Describe the T Flip-Flop and illustrate the different ways of implementing it

Answer 24

 The T(toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together.
 The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate
 The complementing flip-flop is useful for designing binary counters.

*See page 28 and 29

Question 25

Illustrate the characteristic tables and equations of the various flip-flops

Answer 25

*See page 30

Question 26

What is the use of direct inputs in flip-flops

Answer 26

 You can use asynchronous inputs to put a flip-flop to a specific state regardless of the clock
 When power is turned on a digital system, the state of the flip-flops is unknown.
 The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation.

Question 27

Describe the clear or direct reset

Answer 27

 You can clear the content of a flip-flop. The content is changed to zero (0)
 This is called clear or direct reset
 This is particularly useful when the power is off- The state of the flip-flop is set to unknown

Question 28

Illustrate the D Flip-Flop with Asynchronous Reset

Answer 28

*See page 32 and 33

Question 29

What are the different ways of analyzing clocked sequential circuits

Answer 29

 State Equations
 Flip-Flop Input Equations