COMBINATIONAL LOGIC II Flashcards

1
Q

Give an example of an application of the decoder

A

A decoder with an enable input is referred to as a
decoder/demultiplexer.

The truth table of demultiplexer is the same with decoder.
*See notes for image of the demultiplexer

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1
Q

Give an example of an application of the decoder

A

A decoder with an enable input is referred to as a
decoder/demultiplexer.

The truth table of demultiplexer is the same with decoder.
*See notes for image of the demultiplexer

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2
Q

Explain and illustrate a possible way to implement a 4-to-16 decoder

A
  • When w = 0, the top decoder is enabled and the other is disabled.
  • The bottom decoder outputs are all 0’s, and the top eight outputs generate minterms 0000 to 0111.
  • When w = 1, the enable conditions are reversed:
  • The bottom decoder outputs generate minterms 1000 to 1111, while the outputs of the top decoder are all 0’s.

*See page 59

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3
Q

Describe and illustrate the use of a decoder to create a traffic light

A

 Using a 2-4 decoder, the circuit which generates traffic light combinations is as follows.
 To complete the traffic light controller, we just need to
make the inputs i0 and i1 cycle through the binary representations of the numbers 0-3.

*See page 60

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4
Q

Describe what an encoder is and give an example

A

 An encoder is a digital circuit that performs the inverse operation of a decoder.
 An encoder has 2n (or fewer) input lines and n output lines.
 An example of an encoder is the octal-to-binary encoder

*See page 61 for truth table

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5
Q

What are some of the ambiguities of the octal-to-binary encoder

A

 If two inputs are active simultaneously, the output produces an undefined combination e.g D3 and D6 are 1 simultaneously. We can establish an input priority to ensure that only one input is encoded.

 Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated when all the inputs are 0; the output is the same as when D0 is equal to 1.

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6
Q

Describe and illustrate the priority encoder

A

 A priority encoder is an encoder circuit that includes the priority function.
 The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.
- Addresses the ambiguities of the octal-to-binary encoder

*See page 64 for illustration

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7
Q

Describe the functioning of the Valid bit indicator

A

Set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid input and V is equal to 0.

V=0–>no valid inputs
V=1–>valid inputs

*See page 63 and 64

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8
Q

What is the benefit of using don’t care conditions in the truth table of the octal-to-binary truth table

A

 X’s in output columns represent don’t-care conditions
 X’s in the input columns are useful for representing a truth table in condensed form.
 Instead of listing all 16 minterms of four variables.

*See page 63 and 64

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9
Q

How is priority assigned in the priority encoder

A

 The higher the subscript number, the higher the
priority of the input
 Input D3 has the highest priority, so, regardless of the
values of the other inputs

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10
Q

Describe and illustrate the output, truth table and K-Maps of the 7 bit display

A

A more useful application of combinational encoder design is a binary to 7-segment encoder.
*See page 65 and 66

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11
Q

Describe a multiplexer and illustrate its truth table, circuits

A

A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line.

*See page 68

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12
Q

Illustrate:
2-input Multiplexer Design - NAND
4-to-1 Line Multiplexer
4-input Multiplexer Design - NAND

A

*See page 69-71

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13
Q

Describe and illustrate the rotary switch

A

 The rotary switch, also called a wafer switch, is a mechanical device whose input is selected by rotating a
shaft.
 The rotary switch is a manual switch that you can use to select individual data or signal lines simply by turning
its inputs “ON” or “OFF”.

*See page 72

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14
Q

Illustrate boolean function implementation using multiplexers

A

A more efficient method for implementing a Boolean
function of n variables with a multiplexer that has n-1
selection inputs.

*See page 74 and 75

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15
Q

Brush up on BCD arithmetic

A

*See page 45

16
Q

Illustrate the decimal parallel adder

A

 A decimal parallel adder that adds n decimal digits
needs n BCD adder stages.
 The output carry from one stage must be connected
to the input carry of the next higher- order stage.

*See page 47

17
Q

Illustrate the Two-bit by Two-bit Binary Multiplier

A

Usually there are more bits in the partial products and it is necessary to use full adders to produce the sum of the partial products.

*See page 49

18
Q

Illustrate the Four-bit by Three-bit Binary Multiplier

A

 For J multiplier bits and K multiplicand bits we need (J X K) AND gates and (J − 1) K -bit adders to produce a product of J+K bits.
 K=4 and J=3, we need 12 AND gates and two 4-bit adders.

*See page 50