Superscalar Processes Flashcards
A superscalar processor architecture is one in which [x] [y] - [i] [f], [l], [s], [c] - can be initiated [simultaneoulsy] and [e] [i].
common
instructions
integer, floating point arithemtic, load, store, conditional branches
Superscalars are designed to [i] the performance of the [e] of [i]
improve
execution
scalar instructions
Define instruction level parallelism
the degree to which, on average, the instructions of a program can be executed in parall.
A combination of [c] and [h] can be used to [m] instruction-level parallelism.
compiler
hardware techniques
maximise
What are the five limitations to parallelism that a system must cope with?
True data dependency Procuedural depdency Resource conflics Output dependency Antidepdency
True data dependy is also known as
Write read dependency
Instructions following a branch have a [p] on the branch and cannot be [e] until the [b] is [e]
procedural depedency
executed
branch
executed
On a superscalar pipeline, the consequence for a [p] dependency is [s], since a [g] magnitude of [o] is [l] with each delay.
procedural dependency severe greater opportunity lost
If [v] length instructions are used, another sort of [p] can occur. Because the [l] of an [i] is not known, it must be [p] [d] before the [f] instruction can be [f]
variable procedural dependency length instruction partially decoded following fetched
A resource conflict is a [x] of [t] or more [e] for the [c] [r] at the same time.
competition two instructions same resource
Give examples of resources:
memories, caches, busses
Resource conflicts can be [o] by [d] resources.
overcome
duplicating
True data depencies [c] be [o]
cannot
overcome
Instruction level parallelism [e] when [i] in a [s] are [i] and thus can be [e] in [p] by [o]
exists instructures sequence independent executed parallel overlapping
Instruction-level is [d] by the [f] of [t] and [p] in the code
determined
frequency
true data
procedural dependencies
