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Computer Systems > RISC > Flashcards

RISC Flashcards

1
Q

What are the three key elements to be aware of in RISC machines.

A
  1. A limited and simple instruction set.
  2. A large number of general-purpose registers.
  3. An emphasis on optimising the instruction pipeline
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2
Q

What effect did High Level Languages have on processing?

A

They created a semantic gap.

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3
Q

Define semantic gap in terms of computer architecture.

A

The difference beteween the operations provided in high level langagues and those provided in computer architecture.

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4
Q

What issues arise from a semantic gap?

A

Excecution fuck ups
excessive program size
compiler complexity

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5
Q

What was the driving force for CISC machines?

A

Close the semantic gap.

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6
Q

What sort of features did CISC machines have in an attempt to close the semantic gap between high level langauges and the CPU architecture that would have to deal with them?

A

Large number of instructions
Dozens of addressing modes
High level language statements implemented in hardware

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7
Q

Define operations performed in relation to RISC/CISC development.

A

The functions to be performed by the CPU and its interaction with memory

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8
Q

Define operands used in relation to RISC/CISC

A

The types of operands use and their memory organisation for storing them and addressing modes for accessing them.

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9
Q

Define execution sequencing in relation to RISC/CISC

A

The control and pipeline organisation

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10
Q

What are the key things of note from studies of HLL programs?

A

Assignment statements predominate.

Conditional statements are frequent.

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11
Q

If assignment statements are high in HLL, what does this suggest?

A

Data movement is very important

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12
Q

What does a large quantity of conditional statements help to understand?

A

That sequence control of the instruction set is important

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13
Q

What do we understand about variables from Patterson study?

A

Variables are often local and scalar and optimisation on storing and accessing variables is compelling.

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14
Q

What three things did the Patterson study reveal about procedure calls?

A

That they are very time consuming.
The number of parameters and variables a procedure deals affects speed.
Depth of nesting also affects speed.

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15
Q

What is a large number of registers in RISC supposed to support?

A

operand referencing

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16
Q

What is the point of careful attention to design of instruction pipelines?

A

Given the high number of conditional branch calls, a straightforward pipeline will often have a lot of prefetched and then cleared instructions. Things could be better.

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17
Q

What two ways could you attempt to optimise the use of registers?

A

Hardware and software

18
Q

How could software improve register use?

A

Sophisticated analysis of which variables are going to be used most and so keep stuff there.

19
Q

How could hardware be used to improve register use?

A

Simple: profundity of registers = more operands in main memory

20
Q

What happens every time a programe makes a call?

A

Local variables must be moved from registers to main memory
Registers can be reused
Parameters need to be passed

21
Q

Register windows do what?

A

Create register ‘banks’ assigned to different procedure.

Temporary registers overlap to allow for parameter passing.

22
Q

What do register windows not address?

A

The need to store global variables.

23
Q

How are global registers often stored and what ways have been suggested to improve efficency.

A

Allocated by the compiler from main memory to a register.

This is inefficent. Instead, consider set of registers that are ‘global’ and available to all procedures.

24
Q

A program written in a high-level langauge has [x x] references to [x]

A

explicit references

register

25
Q

The object of the compiler is to keep the [x] for as many computations as possible in [y] rather than [z], and to [c] [d] operations

A 
operands
register
main memory
minimise
load and store
26
Q

A compiler assigned a [x] register

A

symbolic

27
Q

If a [c] register does not [y], a [x] register can share the same register

A

symbolic
overlap
procedure

28
Q

Given a graph of nodes and edges, assign colours to nodes such that [c] nodes have different [y]. The [x] of the graph are [c] registers. If two [v] registers are [i] during a problem, an [b] connects them to depict [o].

A 
adjacent
colours
nodes
symbolic
symbolic
live
edge
interference
29
Q

What are the common associations with CISC?

A

That programs are small and that they are fast

30
Q

Why are small programs good?

A

Program takes up less memory. But memory is cheap now. Memory should improve amount of instructions needed but this isn’t likely with CISC with high level of instructions.

31
Q

What about CISC and they greater level of instructions was deemed good for HLL?

A

Motivation is complex HLL operation == quick execution.

But primitive instructions appear to help.

32
Q

What about CISC and they greater level of instructions was deemed good for HLL?

A

Motivation is complex HLL operation == quick execution.

But primitive instructions appear to help.

33
Q

List the characteristics of the RISC architecture.

A
  1. One machine instruction per cycle.
  2. most operations should be register-to-register.
  3. only load and store should access memory
  4. simple addressing modes
  5. simple instruction formats
34
Q

define machine cycle:

A

the time it takes to fetch operations, perform an ALU, store the result.

35
Q

how are most registers addressed in RISC?

A

simple addressing.

36
Q

what are the key characteristics of simple instruction format?

A

Instruction length is fixed

Field locations, especially opcode, are fixed.

37
Q

What are the benefits of the simple instruction format?

A
  1. opcode decoding and register operand accessing can occur at the same time.
  2. Control unit is simpler
  3. Instruction fetching is optimised
  4. Single instruction will not cross page boundaries
38
Q

What are the two phases of the instruction cycle?

A

I: Instruction Fetch
E: Execute. ALU operation (register input and output)

39
Q

What are the three phases for load and storing?

A

I: Instruction Fetch.
E. Execute (calculate memory address)
D: Memory (register to register / memory to register)

40
Q

How does one optimise the pipeline?

A

Code reorgansation.

41
Q

A delayed branch makes use use of a branch that [p x] take effect until [v] the following [i]

A

does not
after
instruction

42
Q

A delayed branch is good for [c]

A

unconditional branch instructions

Computer Systems (17 decks)

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