I/O Flashcards
I/O devices can be split into two categories. What are they?
Block devices
Character devices
A block devise is one that [s] information in [fsb], each one with its own [a]. The essential property of a block device is that it is possible to [r] or [w] each block [i] of all the other ones. [d] are the most common block devices
saves fixed size bits address read write indepently disks
A character device [d] or [a] a [s] of [c], without regard to any [b] structure. It is not [a] and does not have any [s] operation.
delivers accesses stream characters block addressable seek
Give three examples of character device I/O
printers
network intefaces
mice
I/O units typically consist of an [x] component and a [x] compnent.
mechanical
electronic
the electronic component is called the [d] or [a]
device controller
adapter
electronic controllers can handle [m] devices
many
The electronic controller must [a] serial [b] stream to [b] of [b], perform [ec] and [c] with the [c]
convert bit block bytes error correction communicate cpu
electronic controllers typically have a number of [r] where the [o] can command the device to [d] or [a] data or switch itself [ooo].
registers operating system deliver access on or off
The CPU needs to be [a] the device [c] to exchange [d] with them
address
controllers
data
An operating system can only use a [d] if the hardware has a [d] [c]
DMA (direct memory access)
DMA controller
The [d] has [a] to the [s] bus [i] of the CPI.
DMA
access
system
indepent
A DMA has several registers, including a [m], [b] and one or more [c]
memory address regsiter
bute count register
control registers
DMA [c] registers specify the [i] to use, the [d] of transfer, the transfer [u] and the [n] of [b] to transfer in one burst
controller i/o direction unit number bytes
DMA can [c] the flow of [b] between memory and some controller without [c] [c] intervention. The CPU sets up the DMA, telling it how many [b] to [t], the [d] and [ma] involved, and the [d] and let’s it go. When the DMA is [d], it causes an [i], which is handled.
control bytes constant CPU transfer direction memory address direction interrupt
The steps for the DMA.
The [c] programs the [d]
The DMA [c] initates the [t] by issuing a [r] request over the [b] to the [d] controller.
A [w] to [m] occurs
When the write is complete, the [d][c] sends an [as] to the [d][c] over the bus.
DMA controller then [i] the [m] to use and [d] the [b][c]
DMA then [i] the CPU to let it know that the transfer is complete.
When the operating system starts up, it does not have to copy the [db] to [m] because it is already there.
CPU DMA controller transfer read bus disk write memory device controller acknowledgement signal disk controller / DMA controller? increments memory address decrements byte counter interrupts disk block memory
When an [i] device has finished the work given to it, it [c] an [i]. It does this by [a] a [s] on the [b] that it has been [a]. The [s] is detected by the [icc] which decides what to do. If no other [i] are [p], the [ic] processes the interrupt immediately. If another one is in progress, the device is [i] and continues to [a] an [is] on the [b] until is [s] by the CPU.
I/O causes interrupt asserting signal bus assigned signal interrupt controller chip interrupts pending interrupt controller ignored assert interrupt signal bus serviced
to handle an intterupt, an [ic] puts a [n] on the [al] specifying which [d] wants attention and [a] a signal that [i] the CPU
interrupt controller number address lines device asserts interrutps
shortly after it starts running, the [isp] acknowledges the [i] by [w] a [v] to one of the [ic] ports. This means that [ic] is free to make [f] [i]
interrupt service procedure interrupt writing value interrupt controller's further interrupts
Define device indepdence
it should be possible to write programs that can access any I/O device without
