Caches Flashcards
What’s the point of the cache?
To make accessing words faster and to stop always having to request data from main memory
What are the four algorithms for clearing a cache line?
First in first out: FIFO
Last used item
Least frequently used
Random cache clearing
What are some of the key things to think about with cache design
Size of cache
How you map to the cache
How you clear the cache lines
What’s the relationship (in the way data is transferred) between main memory, the cache and the CPU?
Blocks go between the main memory and cache.
Words go between the cache and CPU.
What is the process of if a word is not found in the cache?
The CPU must go to main memory.
The block is delivered from main memory into the cache.
The word is then delivered from the cache into the CPU.
SIGNIFICANT TIME ISSUES THERE
What do you have to consider when an item in the cache has been modified?
You need to denote that the item has been modified in the cache. A ‘dirty bit’.
That item will have to be written back to main memory.
What are the different write policies associated with caches?
Write through
Write back
What is write through?
All write operations to the cache are also made to main memory
What is a potential problem with write through?
Substantial memory traffic and may cause bottleneck.
What is write back?
When an update occurs, an ‘update’ bit is made on the cache line and the data is then written to main memory.
Name two situations where you need to have a write policy.
First: An I/O device could have read/write access to main memory. It could update main memory and cache isn’t. Or flip it: cache could update and the data the I/O device is handling isn’t adjusted accordingly until too late.
Second: multiple CPUs, each with their own cache. If one cache is updated and the others aren’t, it could invalidate the data.
What is a possible when considering writing back to main memory
If more than one device has access to main memory and something is updated in the cache, that means portions of main memory are invalid. Or if an I/O device has updated the word in main memory, then the cache is out of date.
What are three approaches to ensuring cache coherency ?
1) Bus watching with write through
2) Hardware transparency
3) Non-cacheable memory
Explain bus watching with write through policy
Cache controller watches address lines
It detects write operations to main memory
If something is written to shared memory where there is something already in cache, the cache is invalidated
What does bus watching with write through depend on?
That all cache controllers use write through
