Structure and Function of the proccessor Flashcards

1
Q

Control unit

A

The part of the processor that co-ordinates the activity of all other components
Control signals are sent along the control bus between the control unit and the other components of the computer

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2
Q

Controls signals include

A

Memory read-data in adress location to be placed on the data bus
Memory write-data on data bus is written on RAM

Bus request -indicates that a device is requesting the use of the data bus

Bus grant-indicates that the CPU has granted access to the data bus

Clock-used to synchronize operations

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3
Q

ALU

A

Problem solving part of the processor

performs arithmetic,logical and shift operations on data

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4
Q

The accumulator

A

Where the results of the calculation made by the ALU are

All 1/0 geos through accumulator

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5
Q

PC

A

Program counter- keeps track of the memory location of the line of machine code being executed.

Contains the address of the next instruction that is needed to be fetched /carried out

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6
Q

MDR

A

The memory data register stores the data that has been fetched from or stored in memory
copy of MAR
Contains data currently used by the processor

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7
Q

MAR

A

the memory address register stores the address of the data or instructions that are to be fetched from or sent to
copied from PC
address of memory location
may be address of next instruction

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8
Q

CIR

A

Contains the address of the current instruction being executed
its copied from the MDR
It contains data cache and instruction cache

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9
Q

FETCH DECODE EXECUTE cycle:FETCH

A

the address of the next instruction is copied from the PC to the MAR
The instruction held at that address is copied to the MDR simultaneously the content of the PC is incremented so that it holds the address of the next instruction
The contents of the MDR are copied to the CIR

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10
Q

FETCH DECODE EXECUTE cycle:DECODE

A

teh instruction held in teh CIR is decoded.The instruction is split into opcode and operand and teh opcode is used to determine teh type of instruction and what hardware to use to execute it to The operand holds either:
The address of teh data to be used with teh operation,which is then copied to teh MAR or
teh actual data to be operated on,which will be copied to the MDR
The data to be operated in may be passed to teh ALU

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11
Q

FETCH DECODE EXECUTE cycle:EXECUTE

A

The appropriate instruction/opcode is carried out on the operand

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12
Q

What is clock speed?

A

A series of ON/OFF signals used to synchronize the operations of the processor components

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13
Q

How does clock speed affect the processor?

A

Since the Fetch execute cycle is triggered by thr clock pulse of the system clock.The faster the clock speed the faster a computer can fetch decode and execute instructions

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14
Q

What is a dual core processor?

A

A dual-core processor has two processors linked together in the same integrated circuit

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15
Q

How does the number of cores affect the processor?

A

each core is theoretically able to process a different instruction at the same time with its own fetch-execute cycle making a quad core computer two or even four times faster than a single-core computer.

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16
Q

What is cache memory?

A

Cache is a small amount of super-fast (but expensive) memory that stores data and instructions that have recently been used by the processor.

17
Q

Level 1 and 2 cache

A

Level 1 cache is split into instruction and data cache, so that data ad instructions can be fetched simultaneously
level 2 us larger but not as fast as level 1 cache

18
Q

How does cache affect the processor?

A

The more cache memory a computer has ,the more likely it is that it will not have to fetch the next instruction or data form RAM as it will already have been loaded into the super fast cache memory from which it can be retrieved much more quickly

19
Q

What is pipe-lining?

A

Pipe lining is a technique used to improve performance by overlapping stages in the fetch-execute cylcle

20
Q

What is a data bus?

A

it is a bi-directional bus that carriers data between the processor and memory

21
Q

What is a address bus?

A

carries address of the memory location being read from or written to

22
Q

What is a control bus?

A

sends signals from the control unit

23
Q

How does the address bus affect data moving?

A

The width of the address bus dtermines the maximum possible memory address of the system

24
Q

Order of register in the fetch execute cycle

A
PC
MAR
MDR
CIR
ACC