SPLDs, CPLDs, FPGAs

Question 1

What does SPLD stand for?

Answer 1

Simple programmable logic devices

Question 2

What is an SPLD?

Answer 2

This is a chip that has an undefined function when manufactured and are used to implament digital circuits

Question 3

What are some basic parameters of SPLDs?

Answer 3

> Number of gates
Number of IO
Max operating frequency

Question 4

What are the two types of SPLDs?

Answer 4

> Programmable array logic (PAL)

> General array logic (GAL)

Question 5

What is programmable array logic?

Answer 5

> This is an array of fuses, that during programming are broken. The unbroken links allow a SOP expression to be formed
The SOP expression has a limited number of allowed variables
They are only programmable once

Question 6

What is general array logic?

Answer 6

> Fuses are replaced with transistors that are enabled and disabled at startup using an EPROM or S-RAM
They are reprogrammable

Question 7

What is a macrocell?

Answer 7

> The outputs of multiple PAL or GALs are connected to a macrocell
The multiple PALs or GALs are connected together with multiple input OR gates
The macrocell also provides additional output logic
Macrocells are also programmable
[Picture1]

Question 8

What does CPLD stand for?

Answer 8

Complex programmable logic devices

Question 9

What is a CPLD?

Answer 9

> Made from multiple SPLDs connected with a programmable interconnect
This allows them to perform more logic operations that a single SPLD and fit larger digital circuits onto the CPLD

Question 10

What is the arrangement of parts of a CPLD?

Answer 10

> There are multiple LABs (Logic array blocks) connected together using a a PIA (Programmable interconnect arrays)
Each lab is formed of a macrocell and SPLDs
[Picture2]

Question 11

What parts of a CPLD can be programmed?

Answer 11

> The LABs

> The Interconnects

Question 12

How are CPLDs fromgrammed?

Answer 12

> Reprogrammabled

> Using EEPROMS

Question 13

What are the aspects of a CPLD Macrocell?

Answer 13

> 5x 5-input AND gate SPLD (GAL)
A product term selection matrix
Expander

Question 14

What is a product term selection matrix?

Answer 14

This allows different AND gates to be disconnected from the OR gate. For example, if only 3 out of 5 AND gates are used, then they can be disconnected

Question 15

What does having 5 AND gates limit?

Answer 15

It can produce up to 5 product terms for the output. If more are needed then an expander can be used

Question 16

What is a shared expander?

Answer 16

This can feed one (AND gate) output back into the input array

Question 17

What is the benefit of the shared expander?

Answer 17

It avoids replication of terms across the cells and allows SOP expressions with more than 5 inputs to be created

Question 18

What is a parallel expander?

Answer 18

This is where you arrange CPLDs in parallel allowing macrocell 2s output to include the output from macrocell 1

Question 19

What does FPGA stand for?

Answer 19

Field programmable gate array

Question 20

What is an FPGA?

Answer 20

It is similar to a CPLD but has a different architecture.

Question 21

What is the benefit of an FPGA over a CPLD?

Answer 21

An FPGA has many more equivalent gates that can be made from a CPLD

Question 22

What are additional elements that can be included in an FPGA?

Answer 22

> Memory blocks
> Transceivers
> Protcol controllers
> CPUs
> Additional IP

Question 23

What does IP stand for, in terms of FPGA additional circuitry?

Answer 23

Intellectual property

Question 24

What is the benefit of using IP blocks that are unconfigurable?

Answer 24

It removes the need to build everything from scratch

Question 25

What is the overall architecture of an FPGA?

Answer 25

> On the outside are IO blocks
On the inside are configurable logic blocks (CLBs)
Multiple CLBs are connected together with interconnects.
[Picture3]

Question 26

How are CLBs made?

Answer 26

Using multiple logic modules connected with a logical programmable interconnect

Question 27

How are FPGA logic modules programmed?

Answer 27

Using a look up table. this is different than an array.

The look up table is dependent on the SOP expression we want