RTL and FPGA design flow Flashcards
What does RTL stand for?
Register transfer level
What is RTL?
> This is a design abstraction used to define digital circuits as a flow of signals between elements
This is essentially logic diagrams
What are the 6 stages of FPGA design?
- Design Entry
- Functional simulations
- Analysis and syntheseis
- Implamentation
- Timing simulation
- Device programming
What happens in the first stage of the FPGA design process?
Design Entry:
> Describe the digital circuit in a hardware description language e.g. Verilog
What happens in the second stage of the FPGA design process?
Functional simulation:
> Before compiling we want to simulate each part to see how it performs
> We perform simulation manually with external software
> FPGAs cannot be paused for debugging as the circuits are asynchronous
What happens in the thrid stage of the FPGA design process?
Analysis and synthesis:
> Analysis
- Compiler takes each part of the design and testa ll the possible inputs to determine a SOP expression for the output
- This allows minimisation
> Synthesis
- Turns your design into primitives that can be mapped onto an FPGA
What happens in the fourth stage of the FPGA design process?
Implementation:
> No programming occurs
> Uses algorithms to decide how best to fit the synthesised design onto a given FPGA device
> Decides if the design can fit onto the FPGA
- There are a finite number of resources
> The design is then mapped to the physical parts of the chip
- Called placing
> This is where the interconnect programming is computed
What happens in the fifth stage of the FPGA design process?
Timing simulation:
> Simulatio calculate propagation delays for all the parts of the device
> Checks to see if this will be an issue
What happens in the sixth stage of the FPGA design process?
Device programming:
> FPGA is programmed and this physically implaments the program on the FPGA
