Simulation Flashcards

1
Q

What are the two main stages of FPGA design simulation?

A

> Functional simulation: Testing to see if it works as expected
Timing

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2
Q

What is the process of functional simulation?

A

> Simulate each module starting at the bottom of the higherarchy

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3
Q

What is the issue with brute force testing of parts?

A

This is not always feasable as it would take too long on devices with larger number of inputs

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4
Q

What is a critical case?

A

> These are cases that are determined to be critical to the overall functionality
This means you do not need to test all the different inputs but the most important ones

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5
Q

What is the set of tests to be performed called?

A

The test schedule

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6
Q

What sort of test can be performed to accunt for human error?

A

Random testing

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7
Q

What is constrained random testing?

A

This is using random testing and critical case testing in a test schedule

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8
Q

What is a golden module?

A

> This is an ideal version of your device that acts as a simulator for the working version of your design.
You can pass the inputs to both your device under test and the golden model can compare the outputs

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9
Q

What is the command to include timings in your simulation?

A

`timescale 1 ns/100 ps

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10
Q

How are inputs for test benches implamenetd?

A

As registers

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11
Q

What is the initial block?

A

This is the block that runs once at time zero

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12
Q

What does stimuli mean?

A

> This is the test vector

> The inputs to a device

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13
Q

What are the 4 useful functions we can use?

A

$stop; Stops the simulation
$finish; Stops the simulation and closes the simulator
$display(“”); Writes a message to log window
$random; Generates a random number

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14
Q

What does EDA stand for?

A

Electronic Design Automation

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