SLR1 - Structure and Function of the Processor

Question 1

Describe the fetch part of the Fetch-Decode-Execute Cycle.

Answer 1

1. The Program Counter holds the address of the next instruction to be carried out.
2. This address is copied into the MAR
3. The contents of the address in the MAR are copied into the MDR
4. The contents of the MDR are copied into the CIR.
5. The contents of the PC are incremented

Question 2

Describe the Decode part of the Fetch-Decode-Execute Cycle.

Answer 2

6. The contents of the CIR are divided into binary of the operation to be carried out and probably the address of the data that will be used by the program.
7. The control unit then interprets the operation so that the processor knows what to do next.

Question 3

Describe the Execute part of the Fetch-Decode-Execute Cycle.

Answer 3

8. The address part of the instruction is copied from the CIR to the MAR.
9. The data found in the address in the MAR is copied to the MDR.
10. The data is used

Question 4

State and explain the ALU

Answer 4

Arithmetic Logic Unit
Where data is processed and manipulated. Normally consists of arithmetic operations or logical comparisons allowing a program to make decisions.

Question 5

State and explain the CU

Answer 5

Control Unit
The part of the CPU that manages the execution of instructions. It fetches each instruction in sequence and decodes and synchronises it before executing it.

Question 6

State and explain the CIR

Answer 6

Current Instruction Register

A register in the control unit that stores the address of the next instruction currently being executed and decoded.

Question 7

Explain the purpose of registers

Answer 7

Tiny amounts of extremely fast memory located in the CPU normally designed for a specific purpose, where data or or control information is stored temporarily.

Question 8

State and explain the PC

Answer 8

Program Counter

A register in the control unit which holds the address of the next instruction to be executed.

Question 9

Explain the use of the accumulator

Answer 9

A special register within the ALU. It is used to hold the data currently being processed by the central processor.

Question 10

State and explain the MAR

Answer 10

Memory Address Register

A register that stores the address of the memory location currently in use.

Question 11

State and explain the MDR

Answer 11

Memory Data Register
A register in the CPU that stores data being transferred to and from the immediate-access store. It acts as a buffer, allowing the central processor and memory unit to act independently without being affected by minor differences in operation.

Question 12

Describe a bus

Answer 12

A common physical pathway shared by signals to and from several components of a computer.

Question 13

Describe the address bus

Answer 13

The part of the bus which carries identification about where the data is being sent.

Question 14

Describe the data bus

Answer 14

The part of the bus which carries the actual information.

Question 15

Describe the control bus

Answer 15

Carries command and control signals to and from every other component of a computer.

Question 16

Define the clock speed

Answer 16

Cycles per second measured in Hz. The higher the clock speed the faster the computer could work.

Question 17

Describe the Von Neumann Architecture

Answer 17

Traditional computer architecture that forms the basis of most digital systems. A single control unit manages program flow following a linear sequences of fetch-decode-execute.

Question 18

Define and explain the CPU

Answer 18

Central Processing Unit

The main part of the computer, consisting of the registers, ALU and control Unit

Question 19

Define and explain the F-D-E

Answer 19

Fetch-Decode-Execute Cycle
The complete process of retrieving an instruction from store, decoding it and carrying it out. Also known as the instruction cycle.

Question 20

Define Cache

Answer 20

A part of the main store between the central processor and the rest of the memory. It has extremely fast access, so sections of a program and its association data are copied there to take advantage of its short fetch cycle.

Question 21

Describe L1 Cache

Answer 21

Often located directly on the CPU itself, very low capacity, very expensive, typically runs at the same speed as the CPU

Question 22

Describe L2 Cache

Answer 22

Often part of the CPU module, still very expensive, larger capacity, but still less than 1MB, runs at CPU or close to CPU speed.

Question 23

Describe L3 Cache

Answer 23

Often located further away on motherboard, less expensive, large capacity, typically shared between cores.

Question 24

Describe the Harvard Architecture

Answer 24

A computer architecture with physically separate storage and signal pathways for instructions and data.

Question 25

Describe pipelining

Answer 25

The concurrent decoding of two or more machine instructions. While part of one instruction is being decoded, another part of a second instruction may also be decoded.