1.1 Definitions

Question 1

Accumulator

Answer 1

A special register to temporarily store the results of operations performed by the ALU

Question 2

Address Bus

Answer 2

Carries the memory location address of the register the data is being carried to or from.

Question 3

Arithmetic Logic Unit ALU

Answer 3

A part of the CPU that performs arithmetic calculations and logical operations on data for the computer programs

Question 4

Buses

Answer 4

A physical set of parallel wires connecting and carrying groups of bits between several components of a computer.

Question 5

Cache

Answer 5

A small and fast but expensive memory in the CPU used to store instructions and data that are accessed regularly.

Question 6

Clock Speed

Answer 6

The frequency at which the internal clock generates signals switching between 0 and 1. It controls how often instructions are executed and data is fetched.

Question 7

Contemporary Processor Architecture

Answer 7

A modern computer architecture combining elements of both Von Neumann and Harvard architectures.

Question 8

Control Bus

Answer 8

A bi-directional bus carrying control signals from the CU to synchronise access and use of data.

Question 9

Control unit

Answer 9

A part of the CPU that controls and manages the execution of instructions. It sends control signals to coordinate execution and controls Fetch Decode Execute cycles and buses.

Question 10

Current Instruction Register

Answer 10

A special register that stores the current instruction being executed and decoded. The instructions are divided into operand and opcode.

Question 11

Data Bus

Answer 11

A bi-directional bus for carrying data and instructions between the processor and memory.

Question 12

Fetch Decode Execute cycle

Answer 12

The process of fetching from memory (supplying the address and retrieving the instruction from memory), decoding (interpreting the instruction and then reading and retrieving the required data from their addresses) and executing the instruction. (CPU carries out the required actions)

Question 13

Harvard Architecture

Answer 13

A computer architecture that stores data and instructions in separate memories to allow the next instruction to be read while data is currently being read or written.

Question 14

Memory Address Register MAR

Answer 14

A special register that stores the memory address of the next instruction to load or data to use

Question 15

Memory Data Register MDR

Answer 15

A special register that temporarily stores data to be read from or written to the computer’s memory

Question 16

Number of Cores

Answer 16

A core is a processing unit that handles instructions with its own fetch execute decode cycles. Multi-core processors have multiple cores that can run simultaneously.

Question 17

Pipelining

Answer 17

The simultaneous decoding of several instructions by decoding the next instruction and fetching the one after while the current one is being doubled.

Question 18

Program Counter

Answer 18

A special purpose register that stores the address of the next instruction to be executed.

Question 19

Registers

Answer 19

Special memory cells that can be accessed quickly. They temporarily store data and control information.

Question 20

Von Neumann Architecture

Answer 20

A computer architecture where a single control unit manages program control via a linear sequence of fetch decode execute cycles.

Question 21

Start at 1.2.1

Answer 21

1.2.1