Mid-term Study Flashcards
For decimal encoding, what exponents values are reserved?
00000000 and 11111111
What are the general types of ISA commands on the CPU?
- Data processing (AND, NOT)
- Data movement (LD, LEA)
- Control Instructions (JMP, BRP)
- I/O Instructions (getc)
What is CISC and RISC what are their differences?
CISC - Complex Instruction Set Computer
- Robust instructions, reduced ASM
- Can op directly on data
- Translating from high level languages is easier
- Con - Lots of unused instructions
RISC - Reduced Instruction Set Computer
- Single clock-cycle instructions (very simple)
- Can only LD and ST directly on data
- ALU only works on registers
- Allows for super efficiency (pipelining)
- Con - results in complex ASM
What is the address space for LS3 and what does that mean?
Address space is 216 (16 bit addresses)
Each memory locations holds a 16-bit value
Draw the diagram of the LC3 memory layout
What LC3 registered are not directly accessible?
- PC - What line of code we are on
- IR - Currently instruction executed
- CC - Used to for loops
What are the first 4 bits of an LC3 instruction for?
The opcode
What are the addressing modes that LC-3 supports?
What are the assembler directives?
What are the traps in LC3?
What happens during the first and second pass of LC3 assembly?
First pass:
- symbol table created for labels
Second pass:
- symbols are used to build machine languages and the following files are output
- .sym
- .hex
- .bin
- .asm
- .lst (file list)
What are the instructions that affect conditions codes?
- ADD
- AND
- LD
- LDI
- LEA
- NOT
What are the limitations of branching, and how can those limitations be circumvented?
Branching is PC-relative
- The offset is added to the PC counter for the new mem location
- This offset is 9 bits (limited to -255 to 256 memory space)
One can use JMP to circumvent this (and jump anywhere in memory space)
- Store new memory address in variable
- LEA variable into a register
- Use the register to JMP
- JMP R1
What are the 5 addressing modes that LC3 supports?
- Immediate
- Register
- Direct (or PC-Relative)
- Indirect
- Relative (or base+offset)
How do you calculate the EA of Direct(Pc-Relative) mode?
It loads or stores the data in:
Reg <–> M[(PC)+SEXT(IR[8:0])]
OP Codes:
LD [0010][Dst][PCoffset9]
ST [0011][Src][PCoffset9]
The range can be (pc) - 256 <= x <= 255 + (pc)
How do you calculate the EA of Indirect mode?
REG<–> M[M[(PC)+SEXT(IR[8:0])]]
or more simply:
REG <–>M[m[data]]
The memory at the memory location
LDI [1010][Dst][PCoffset9]
STI [1011][Src][PCoffset9]
How do you calculate the EA of Load Effective Address (LEA)?
it is used in the same way LD is, to load the base address of a locaiton (Used for arrays)
How do you calculate the EA of base + offset mode?
LEA loads the base into a register, then offset is used to access the i-th element.
This is limited to
EA = BaseReg + SEXT(IR[5:0])
LDR [0110][Dst][Base][offset6]
STR [0111][Src][Base][offset6]
The offset must be between -32 and +31
What is a level-sensitive D Latch?
Draw it’s truth table.
It is an improvement on a latch, because a d latch has undefined output is S=1, R=1 and will oscilate if it is then set to S=0,R=0.
A level-sensitive D latch prevents this from occuring. As the E input acts as the S/R. When E is 1 -> write, when E is 0 -> read, there are no other options
In general, how are D latches combined to create a register?
Holds a fixed multi-bit value
An n-level sensitive d latches = n-bit register
When E = 1 the values of D3,D2,D1,D0 are stored
When E = 0 the values of D3,D2,D1,D0 are read
E = 1 acts as set
E = 0 acts as reset
What is address space?
Addressible locations of the memory
n-bit address = 2n distinct addresses
A word is the size of a quantity that is processed by the ALU
Usually matches the size of an addressable memory location
Example
A 24 bit address can address 224 memory locations
If each location holds 1 byte (8 bits) then the memory size is 16mb
1 MB = 220 bytes (slightly larger than 1 million bytes)
If each location contains 4 bytes(32 bits) then it is 64MB
LC-3 word is 16bits which is the size of a register and the size of an addressable memory location
What is addressibility?
What is the difference between byte addressable and word addressible?
Byte addressable = each memory location holds 8 bits (one byte)
Word addressable = each memory location holds a full standard word
A whole word is written to and read from memory in one operation
Byte Addressable = uses a multi-vyte word, using Endian it either starts at MSB or LSB
Word Addressable = A single address location
What is Endian.
Give examples using the following 32-bit word
0xe543a46f
Used for byte addressability.
The type of endian determines if the address space starts at the MSB or LSB.
Big Endian = starts at memory loc of MSB
Little Endian = starts at memory loc of LSB (and build backwards)
