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Comp 2280 Comp Sys > Mid-term Study > Flashcards

Mid-term Study Flashcards

1
Q

For decimal encoding, what exponents values are reserved?

A

00000000 and 11111111

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2
Q

What are the general types of ISA commands on the CPU?

A
  • Data processing (AND, NOT)
  • Data movement (LD, LEA)
  • Control Instructions (JMP, BRP)
  • I/O Instructions (getc)
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3
Q

What is CISC and RISC what are their differences?

A

CISC - Complex Instruction Set Computer

  • Robust instructions, reduced ASM
  • Can op directly on data
  • Translating from high level languages is easier
  • Con - Lots of unused instructions

RISC - Reduced Instruction Set Computer

  • Single clock-cycle instructions (very simple)
  • Can only LD and ST directly on data
  • ALU only works on registers
  • Allows for super efficiency (pipelining)
  • Con - results in complex ASM
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4
Q

What is the address space for LS3 and what does that mean?

A

Address space is 216 (16 bit addresses)

Each memory locations holds a 16-bit value

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5
Q

Draw the diagram of the LC3 memory layout

A
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6
Q

What LC3 registered are not directly accessible?

A
  • PC - What line of code we are on
  • IR - Currently instruction executed
  • CC - Used to for loops
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7
Q

What are the first 4 bits of an LC3 instruction for?

A

The opcode

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8
Q

What are the addressing modes that LC-3 supports?

A
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9
Q

What are the assembler directives?

A
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10
Q

What are the traps in LC3?

A
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11
Q

What happens during the first and second pass of LC3 assembly?

A

First pass:

  • symbol table created for labels

Second pass:

  • symbols are used to build machine languages and the following files are output
    • .sym
    • .hex
    • .bin
    • .asm
    • .lst (file list)
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12
Q

What are the instructions that affect conditions codes?

A
  • ADD
  • AND
  • LD
  • LDI
  • LEA
  • NOT
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13
Q

What are the limitations of branching, and how can those limitations be circumvented?

A

Branching is PC-relative

  • The offset is added to the PC counter for the new mem location
    • This offset is 9 bits (limited to -255 to 256 memory space)

One can use JMP to circumvent this (and jump anywhere in memory space)

  1. Store new memory address in variable
  2. LEA variable into a register
  3. Use the register to JMP
    • JMP R1
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14
Q

What are the 5 addressing modes that LC3 supports?

A
  1. Immediate
  2. Register
  3. Direct (or PC-Relative)
  4. Indirect
  5. Relative (or base+offset)
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15
Q

How do you calculate the EA of Direct(Pc-Relative) mode?

A

It loads or stores the data in:

Reg <–> M[(PC)+SEXT(IR[8:0])]

OP Codes:

LD [0010][Dst][PCoffset9]

ST [0011][Src][PCoffset9]

The range can be (pc) - 256 <= x <= 255 + (pc)

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16
Q

How do you calculate the EA of Indirect mode?

A

REG<–> M[M[(PC)+SEXT(IR[8:0])]]

or more simply:

REG <–>M[m[data]]

The memory at the memory location

LDI [1010][Dst][PCoffset9]

STI [1011][Src][PCoffset9]

17
Q

How do you calculate the EA of Load Effective Address (LEA)?

A

it is used in the same way LD is, to load the base address of a locaiton (Used for arrays)

18
Q

How do you calculate the EA of base + offset mode?

A

LEA loads the base into a register, then offset is used to access the i-th element.

This is limited to

EA = BaseReg + SEXT(IR[5:0])

LDR [0110][Dst][Base][offset6]

STR [0111][Src][Base][offset6]

The offset must be between -32 and +31

19
Q

What is a level-sensitive D Latch?

Draw it’s truth table.

A

It is an improvement on a latch, because a d latch has undefined output is S=1, R=1 and will oscilate if it is then set to S=0,R=0.

A level-sensitive D latch prevents this from occuring. As the E input acts as the S/R. When E is 1 -> write, when E is 0 -> read, there are no other options

20
Q

In general, how are D latches combined to create a register?

A

Holds a fixed multi-bit value

An n-level sensitive d latches = n-bit register

When E = 1 the values of D3,D2,D1,D0 are stored

When E = 0 the values of D3,D2,D1,D0 are read

E = 1 acts as set

E = 0 acts as reset

21
Q

What is address space?

A

Addressible locations of the memory

n-bit address = 2n distinct addresses

A word is the size of a quantity that is processed by the ALU

Usually matches the size of an addressable memory location

Example

A 24 bit address can address 224 memory locations

If each location holds 1 byte (8 bits) then the memory size is 16mb

1 MB = 220 bytes (slightly larger than 1 million bytes)

If each location contains 4 bytes(32 bits) then it is 64MB

LC-3 word is 16bits which is the size of a register and the size of an addressable memory location

22
Q

What is addressibility?

What is the difference between byte addressable and word addressible?

A

Byte addressable = each memory location holds 8 bits (one byte)

Word addressable = each memory location holds a full standard word

A whole word is written to and read from memory in one operation

Byte Addressable = uses a multi-vyte word, using Endian it either starts at MSB or LSB

Word Addressable = A single address location

23
Q

What is Endian.

Give examples using the following 32-bit word

0xe543a46f

A

Used for byte addressability.

The type of endian determines if the address space starts at the MSB or LSB.

Big Endian = starts at memory loc of MSB

Little Endian = starts at memory loc of LSB (and build backwards)

Comp 2280 Comp Sys (10 decks)

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