General Compare and Contrast Sht

Question 1

State the main difference between the von Neumann architechture and the Harvard architecture

Answer 1

The main difference is the harvard architecture has seperate memories for instructions and data and hence sereate busses to access these 2 memories, while a von Neuman architecture has a single memeory for storing both programs and data.

Advantage of Von Neumann:

• Only on main memory and can be entirely used by a program
• Having one bus leads to simpler and cost-effective control unit
• Data and instructions are accessed in the same way

Advantage of Harvard

• Two buses can theoretically lead to execution that is twice as fast
• Memories for data and instruction can be of different technologies and siezes
• Safe in the sense that a program cannot overwrite itself

Question 2

What is the general instruction cycle?

Answer 2

Question 3

Compare/Contrast CISC vs RISC

Answer 3

CISC - Complex Instruction Set Computer

Large collection of instructions with lots of addressing modes

Primary Goal: use as few lines of assembly languages instructions as possible to complete a task

Advantage: makes translating from high-level languages to assembly easier

Disadvantage: only a very small subset of the instructions will be used in a typical program

RISC - Reduced instruction set computer

small collection of instructions with few adressing modes

Uses only simple instructions that can be in a single clock cycle

Advantage: pipelining can be used to improve performance (because each insrtruction requires one clock cycle)

Disadvantage: It’s more difficult to write code for, due to limited instruction set and addressing modes and assembly language programs tend to be longer than those written for a CISC architecture

Question 4

What are the following traps?

Answer 4

Question 5

What is done on each pass of the compiler?

Answer 5

First pass:

Symbol table created, used on the 2nd pass to “fill in” the label references

Second pass:

• Each line scanned again
• Translated assembly lang to machine lang
  
  • find the right opcode for the instruction
  • look up symbls in the symbol table as necessary
  • determine operand field for the instruction
• Fill memory locs

Question 6

What are the instructions that affect condition codes?

Answer 6

Add, And, ld, ldi, ldr, lea, not

Question 7

What is the difference between JMP and the various forms of branching?

Answer 7

JMP can go beyond the -255 to 256 distance from PC (ask compared to BR)

JMP can jump to anywhere in the memory space

Example:

LEA R4, EXIT

JMP R4

Question 8

What is the difference between combination and sequential circuits?

Answer 8

Combinational:

Circuits whose output dpeends only on the current inputs

Sequential:

circuits whose output depends on the current inputs and it’s current state.

Question 9

What is a decoder?

Answer 9

A n-bit decoder has n inputs and 2ⁿ outputs

Exactly one output is set to 1 for each input pattern

Think of n inputs as encoding an unsigned number j and k^th output is 1 if and only if k = j

Useful for selecting or activating one of many components based on a bit pattern.

Question 10

What would an encoder do with 3 inputs?

Answer 10

The 3 inputs would represent a 3 bit number.

The outputs would be labeled 0 through to 7 (the binary representations)

Question 11

Create a decoder for this circuit:

Answer 11

Question 12

What is a multiplexor and what is it used for?

Answer 12

Inputs:

n-bit selector S₀,S₁,…S_n-1

2ⁿ “data” inputs D₀,D₁,…D_2ⁿ-1

Output:

one of the 2ⁿ inputs determined by the n-bit

If S_n-1S_n-2…S₁S₀ = k using unsigned encoding, then the output is the input value D_k

Uses:

select oninput from multiples

Select which computed value to pass to the next stage

Question 13

What is the difference between a decoder and a multiplexer?

Answer 13

A decoder takes two bits and has 2^n out puts

We make an unsigned number with the selector bits and output the number that it represents

A multiplexor takes this concept but adds an additional input into the gate so that when the number is outputted the actual output is the 1/4 outputs

Question 14

What is the difference between active high and active low?

Answer 14

Question 15

What is an S-R latch and how does it work?

Answer 15

It is important that we do not set the latch to S=1 and R=1

It will just oscilate!

Question 16

Provide the truth table for a S-R latch

Answer 16

Question 17

What is the different between an S-R Latch and a D latch

Answer 17

S-R latch:

Should never set R=1, S=1

D-latch:

Is an S-R latch with additional logic with a new input signal.

WE, outputs can be set/reset only when WE=1 (know as level sensitive)

The S-R inputs are replaced with a single input D

Question 18

What is a D-latch and how does it work?

Provide the truth table

What is a problem with using D latches?

Answer 18

It’s an S-R latch with extra logic.

Inputs S-R are now replaced by WE and D as our input to let through or not let through

• When E= 0, the latch holds its current value
• When E=1, the output of the 2 AND gates depends on D
  
  • When D=1 it has the effect of S=1, R=0
  • When D=0 it has the effect of S=0, R=1

Problem:

If we have a sequence of D lathces where the output of one latch is used as input for another latch and they all share a common E (enable) input signal

If a clock used as E input signal, the input value going into the first latch can get propagated to other latches if the clock holds its value at 1 for too long of a duration

This is a real problem in when the system is synchronous, like a CPU

Question 19

What is:

• Address Space

Answer 19

Address Space:

• is the adressable locations of the memory
• Given an n-bit address, 2ⁿ distinct addresses may be specificied
  
  • If each location holds 1 byte (= 8 bits) than the mem size is 16mb
  • Ieach locations holds 4 bytes (= 32 bits) than the mem size is 64mb
• A word is the size of a quantitity that is processed by the ALU

Question 20

What is addressibility?

Answer 20

• Computers are either byte or word addressable
• Each memory location holds either 8 bits (1 byte) or a full standard word for that computer
• In computers a whole word is written to and read from memory in one oepration, even if comp is byte-addressable
  Endian

Question 21

What is endian?

Answer 21

Specififies how a (multi-byte) word is stored in a byte-addressable computer
Two possibilities:

• Big endian - The MSB of the word is stored at the specificed address
• Little endian - The LSB of the wor is stored at the specified address

Question 22

What are the attributes a FSM has?

Answer 22

A finite state machine state transition are only possible on positive clock edges

Question 23

What are the general steps to building a circuit for a FSM?

Answer 23

Question 24

What building a FSM circuit

What do we make from the truth table?

What do we make from the state transition table?

Answer 24

Truth table = outputs

Statetransition table = next state

Question 25

What is the difference between:

S-R Latch

D Latch

D FlipFlop

Answer 25

S-R:

S=1,R=0 - set the input to 1

S=0,R=1 - reset to zero

S=0,R=0 - hold current value

S=1,R=1 - Is bad MMk

D-latch:

Same as S-R, but now we have extra logic and have

D input and E (or WE)

When E is enabled we set whatever D is.

When E is disabled, it just holds current value

Things change entirely dependant on E.

D Flip-Flop:

It is the same as a D-latch, but there are two chained and the enable is effectively a clock and changes only occur on a rising clock edge

Question 26

What is the symbol for a D flip-flop?

Answer 26

The only difference between this symbol and a D-latch is the invesion on E.

Question 27

What does a device controller contain?

Answer 27

A device controller contains the following:

• Control/Status Registers:
  
  • CPU tells device what operations to perform by writing to control register(s)..
  • CPU checks the status of an operation by reading status register(s)
• Data Registers - used by CPU to transfer data to/from device
• Device Electronics
  
  • this performs the actual operations on the device
  • for example, pixels to screen, bits to/from disk, characters from keyboard

Question 28

What is port-mapped IO?

Answer 28

CPU has direct access to the device registers

has seperate address space from main memory

There is dedicated instructions for accessing device registers

Question 29

What is memory-mapped IO?

Answer 29

Assign a main memory address to each device registers

use existing data movement instructions (LD, ST) to access the device registers

Not actually accessing RAM, but instead these addresses map to device registers

Question 30

What is the pros/cons of Port-mapped/Memory Mapped IO?

Answer 30

Benenfits of dedicated port-mapped IO

• Doesn’t use up any (main) memory locations

Benefits of memory mapped IO

• Regular memory instruction can be used along with the addressing modes associated with these instructions
• Less complex than dedicated IO instructions

Question 31

With regard to CPU data timing

What is the difference between Synchonous transfer and Asynchronous transfer?

Answer 31

Synchronous transfer

• data is supplied at a known fixed rate
• CPU reads/write every X cycles, where X is pre-determined

Asynchronous transfer

• data rate is less predicatable
• CPU must synchronize with device, so that it doesn’t miss data or write too quickly
• This can be done using the status registers of the device.

Question 32

What is the difference between polling and interrupts?

Answer 32

Question 33

In general, how does polling work for the keyboard in LC-3?

Answer 33

Question 34

Why would interupts be better than polling?

Answer 34

Question 35

How does an interupt work with a device?

Answer 35

Question 36

What must the CPU do when it runs an interrupt service routine?

Answer 36

Question 37

What state information needs to be saved by the CPU when it need to execute an ISR?

Answer 37

Question 38

What is the supervisor stack in LC-3?

Where is the supervisor stack pointer saved, where is the User stack saved?

Answer 38

Supervisor mode grants the program control of all functions of the machine.

When switched over to supervisor mode, it uses a new stack, the supervisor stack.

Normally we use R6 to keep track of the user stack. LC-3 does not use an actual seperate stack, it layers on top of the user stack.

So when supervisor mode is engaged, the user stack is in R6 is saved to save.USP and R6 is loaded with saved.SSP and vice versa

Supervisor stack saved: saved.SSP

User stack is saved: saved.USP

Question 39

What is the general process that occurs when CPU is about to invoke an ISR?

Answer 39

Question 40

Whats the difference between an ISR and a regular subroutine?

Answer 40

It executes in supervisor mode whereas regular subroutines execute in user mode

ISRs are called by the CPU to handle an interrupt service request whereas regular subroutines are called by other user code

An ISR executes the instruction RTI when it is finished whereas a reguar subroutine executes the instruction RET when it is finished.

Question 41

What happens when RTI is called by an ISR?

Answer 41

Question 42

What are the components involved in executing traps?

Answer 42

Question 43

What is the run latch? How does it relate to Trap x25?

Answer 43