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CSA (LAB) > M3 > Flashcards

M3 Flashcards

1
Q

refers to the way in which the operand of an instruction is specified.

A

Addressing modes

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2
Q

specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually executed.

A

Addressing modes

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3
Q

is an 8 bit or 16 bit immediate value given in the instruction.

A

Displacement

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4
Q

is an addressing mode wherein the operand is specified in the instruction
itself.

A

implied mode

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5
Q

this mode the data is 8 bits or 16 bits long and data is the part of instruction.

A

Implied mode

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6
Q

In this mode, the operand is placed in one of 8 bit or 16 bit general purpose
registers.

A

Register mode.

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7
Q

In this, addressing the operand’s offset is placed in any one of the registers BX,BP,SI,DI as specified in the instruction

A

Register Indirect mode.

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8
Q

After accessing the operand, the contents of this register are
automatically incremented to point to the next consecutive memory location.(R1)+

A

Auto Indexed increment.

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9
Q

Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive memory location. –(R1)

A

Auto indexed decrement.

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10
Q

is also referred to as Absolute addressing Mode.

A

Direct addressing

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11
Q

is also referred to as Direct addressing.

A

Absolute addressing Mode

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12
Q

In this addressing mode the 16 bit effective address of the

data is the part of the instruction.

A

Absolute addressing Mode.

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13
Q

In this mode effective address is in the register, and corresponding
register name will be maintained in the address field of an instruction.

A

register Indirect.

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14
Q

In this mode effective address is in the memory, and corresponding
memory address will be maintained in the address field of an instruction.

A

Memory Indirect.

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15
Q

In this mode effective address is obtained by adding
displacement to PC

A

PC relative addressing mode.

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16
Q

In this mode effective address is obtained by adding base

register value to address field value.

A

Base register addressing mode.

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17
Q

X in the immediate mode is that the range of constants are restricted by size of
address field.

A

Limitation

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18
Q

are designed with implied addressing mode

A

Zero address instruction

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19
Q

Addressing modes for 8086 instructions are divided into X categories

A

2

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20
Q

The X provide flexible access to memory, allowing you to

easily access variables, arrays, records, pointers, and other complex data types.

A

8086 memory addressing modes

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21
Q

The key to good assembly language programming is the proper use of X

A

memory addressing

modes.

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22
Q

The term X refers to the way in which the operand of an instruction is
specified

A

addressing modes

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23
Q

specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually executed

A

addressing mode

24
Q

Two categories of addressing modes for 8086 instructions.

A

Addressing modes for data and Addressing modes for branch

25
Q

Two parts of an assembly language program instruction

A

Opcode and Operand

26
Q

Two components of the memory address of an operand?

A

Starting address and offset

27
Q

In X addressing the operand is specified in the instruction itself.

A

implied

28
Q

is the symbol used for Absolute addressing Mode?

A

[]

29
Q

X memory reference is required to access the data in a memory indirect mode.

A

Two

30
Q

In a X mode, one register reference, one memory reference is required to
access the data.

A

Register indirect

31
Q

In this addressing mode, the operand’s offset is sum of the

content of a base register BX and an index register SI.

A

Based index addressing.

32
Q

provides a powerful memory management mechanism.

A

Segmentation

33
Q

allows programmers to partition their programs into modules that operate
independently of one another.

A

Segmentation

34
Q

provides a way to easily implement object-oriented programs

A

Segments

35
Q

allows two processes to easily share data.

A

Segments

36
Q

is the simplest partitioning method.

A

Fixed Partitioning

37
Q

is a type of partitioning wherein the main memory portion for user applications
is initially a single contiguous block.

A

Dynamic

38
Q

is a unique location in primary storage (or main memory) that serves as a
reference point for other memory locations called absolute addresses.

A

Base Address

39
Q

is identified by a segment (its base address) and an offset

A

Logical Address

40
Q

identifies the distance in bytes that the storage location of interest resides from
this starting address.

A

Offset

41
Q

is an address that is generated by CPU while a program is running.

A

Logical Address

42
Q

is an address that does not exist physically, therefore, it is also known as
Virtual

A

Logical Address

43
Q

is used as a reference to access the physical memory location by CPU

A

Logical Address

44
Q

is the set of all logical addresses generated by a program’s
perspective.

A

Logical address space

45
Q

is used for mapping logical address to its corresponding
physical address

A

Memory-Management Unit

46
Q

identifies a physical location of required data in a memory.

A

Physical Address

47
Q

is used for all physical addresses corresponding to the logical
addresses in a Logical address space.

A

Physical Address Space

48
Q

is an address generated by the CPU.

A

Logical Address

49
Q

is a memory management scheme that eliminates the need for contiguous
allocation of physical memory.

A

Paging

50
Q

The mapping from virtual to physical address is done

by this hardware device.

A

memory management unit (MMU).

51
Q

is the mapping from virtual to physical address.

A

paging technique

52
Q

is conceptually divided into a number of fixed-size blocks,
called frames

A

The Physical Address Space

53
Q

is also divided into fixed-size blocks, called Pages

A

The Logical address Space

54
Q

refers to the number of bits required to represent the pages in Logical
Address Space.

A

Page Number

55
Q

is the number of bits required to represent particular word in a page

A

Offset

56
Q

is the number of bits required to represent the frame of Physical Address
Space

A

Frame number

57
Q

is the number of bits required to represent particular word in a frame

A

Frame offset

CSA (LAB) (5 decks)

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